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sh69p55a/k55a otp/mask 8k 4-bit micro-controller with lcd driver & 10-bit sar adc 1 v2.1 features ? sh6610d-based single-chip 4-bit micro-controller with lcd driver & 10-bit sar adc ? otp rom: 8k x 16 bits (sh69p55a) ? mask rom: 8k x 16 bits (SH69K55A) ? ram: 515x 4 bits - 99 system control register - 376 data memory - 40 lcd ram ? operation voltage: 2.4v - 5.5v - f osc = 30k- 4mhz, v dd = 2.4v - 5.5v - f osc = 30k - 8mhz, v dd = 4.5v - 5.5v ? 42 cmos bi-directional i/o pins (including one open-drain output portc.3) ? built-in pull-high resistor for porta - portk ? 8-level stack (including interrupts) ? two 8-bit and one 16-bit auto re-loaded timer/counter ? lcd driver: - 16 seg x 8 com (1/8 duty, 1/4 bias) - 18 seg x 6 com (1/6 duty, 1/3 bias) - 20 seg x 4 com (1/4 duty, 1/3 bias) ? led driver: - 8 seg x 6 com (1/6 duty) - 8 seg x 5 com (1/5 duty) - 8 seg x 4 com (1/4 duty) ? powerful interrupt sources: - timer0 interrupt - timer1 interrupt - timer2 interrupt - external interrupts (portb & portc falling edge interrupts, a/d interrupt, key scan interrupt) ? oscillator (code option) - crystal oscillator: 32.768khz, 400khz - 8mhz - ceramic resonator: 400khz - 8mhz - external rc oscillator: 400khz - 8mhz - internal rc oscillator: 4mhz 5% ? one built-in pll oscillator (1, 2, 4, 8mhz) ? instruction cycle time (4/f osc ) ? 10 channels 10-bit resolution analog/digital converter (adc) ? 2 channel tone generators ? built-in automatic key scanner ? zero cross detect function for ac power line ? read rom data table function (rdt) ? one channel 8+2bit pwm output ? reset - built-in watchdog timer (wdt) [(code option)] - built-in power-on reset (por) - built-in low voltage reset (lvr) [(code option)] ? two-level low voltage reset (lvr) (code option) ? two low power operation modes: halt and stop ? otp type/code protection (sh69p55a) ? mask type (SH69K55A) ? 28-pin sop package; 44-pin qfp package; 32-pin dip package general description sh69p55a/69k55a is a single-chip 4-bit micro-controller. this device integrates a sh6610d cpu core, ram, rom, timer, lcd/led driver, i/o ports, watchdog timer, 10 channels 10-bit resolution adc, low voltage re set, automatic key scan, pll and zero cross detect function. the sh69p55a/69k55a is su itable for washing machine and micro-wave oven etc. application. http://www.xinpian.net ceo??rg??[?0ic??[?0surgg:??[?g r? 010-62245566 13810019655
sh69p55a/k55a 2 pin configuration (44 pin) gnd v dd porta.0/seg1/led_s1/key_i1 porta.2/seg3/led_s3/key_i3 porta.3/seg4/led_s4/key_i4 portf.0/seg5/led_s5/key_i5 portf.1/seg6/led_s6 portf.3/seg8/led_s8 porti.0/seg9 25 24 23 32 31 30 29 28 27 26 1234567891011 33 12 13 14 15 16 17 18 19 22 21 20 sh69p55a/69k55a /44 pin portc.0/pll_c osco/portc.1 osci/portc.2 porte.3/com5/led_c5/seg20 porte.2/com6/led_c6/seg19 porte.1/com7/seg18 porte.0/com8/seg17 porth.3/seg16 porth.2/seg15 porth.1/seg14 porth.0/seg13 porti.3/seg12 porti.2/seg11 porti.1/seg10 44 43 42 41 40 39 38 37 34 35 36 portk.1 portk.0 portf.2/seg7/led_s7 porta.1/seg2/led_s2/key_i2 reset/portc.3 portd.0/com4/led_c4/key_04 portd.1/com3/led_c3/key_03 portd.2/com2/led_c2/key_02 portd.3/com1/led_c1/key_01 portb.1/an1 portb.2/an2 portb.3/an3 portg.0/pwm portg.1/tone/an9 portg.2/v ref /t0 portg.3/t2/an8 portj.0/an4 portj.1/an5 portj.2/an6 portj.3/an7 portb.0/an0 http://www.xinpian.net ceo??rg??[?0ic??[?0surgg:??[?g r? 010-62245566 13810019655
sh69p55a/k55a 3 pin configuration (32 pin & 28 pin) sh69p55a/69k55a /32pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 v dd gnd portf.0/seg5/key_i5/led_s5 porth.2/seg15 portf.3/seg8/led_s8 portf.2/seg7/led_s7 portf.1/seg6/led_s6 portd.0/com4/led_c4/key_o4 porte.3/com5/seg20/led_c5 porte.2/com6/seg19/led_c6 porth.3/seg16 portd.3/com1/led_c1/key_o1 portd.2/com2/led_c2/key_o2 portd.1/com3/led_c3/key_o3 porta.2/seg3/key_i3/led_s3 porta.3/seg4/key_i4/led_s4 porte.1/com7/seg18 porte.0/com8/seg17 portb.1/an1 portb.2/an2 portb.3/an3 portg.0/pwm portg.1/tone/an9 portg.2/vref/t0 portb.0/an0 portc.0/pll_c osco/portc.1 osci/portc.2 portg.3/t2/an8 reset/portc.3 porta.0/seg1/led_s1/key_i1 porta.1/seg2/led_s2/key_i2 sh69p55a/69k55a /28pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 porta.3/seg4/led_s4 porti.0/seg9 portb.2/an2 portb.1/an1 portb.0/an0 porta.1/seg2/led_s2 porta.2/seg3/led_s3 porti.1/seg10 porta.0/seg1/led_s1 v dd portc.0/pll_c portg.3/t2/an8 gnd portj.1/an5 portj.2/an6 portj.3/an7 portj.0/an4 porte.3/com5/led_c5 porte.2/com6/led_c6 porte.1/com7 porte.0/com8 reset/portc.3 osco/portc.1 osci/portc.2 portb.3/an3 portg.0/pwm portg.1/tone/an9 portg.2/vref/t0 http://www.xinpian.net ceo??rg??[?0ic??[?0surgg:??[?g r? 010-62245566 13810019655
sh69p55a/k55a 4 block diagram portj.3 - 0/an7 - an4 oscillator cpu wdt rc portb (4-bit) portf (4-bit) rom 8196 x 16 bits ram 99 x 4 bits system register watch dog timer porte (4-bit) reset circuit osci/portc.2 osco/portc.1 v dd gnd reset/portc.3 porta (4-bit) portd (4-bit) portd.3 - 0/com1 - com4/ led_c1 - led_c4/ key_o1 - key_o4 376 x 4 bits data memory 10ch x 10bits adc 1 x ( 8+2) bits pwm power circuit portb.3 - 0/an3 - an0 portf.3 - 0/seg8 - seg5/ led_s8 - led_s5/key_i5 porte.3 - 0/com5 - com8/ led_c5 - led_c6/ seg20 - seg17 porta.3 - 0/seg4 - seg1/ led_s4 - led_s1/ key_i4 - key_i1 porth (4-bit) portc.3 porth.3 - 0/seg16 - seg13 tone generator 1 portc.2 - 0 tone generator 2 portg.3 - 0/t2, t0, v ref / tone/pwm/an8 - an9 portg (4-bit) porti.3 - 0/seg12 - seg9 porti (4-bit) portj (4-bit) portk (2-bit) portk.1 - 0 portc.0/pll_c timer 0 (8 bits) timer1 (8 bits) timer2 (16 bits) 40x 4 bits lcd ram http://www.xinpian.net ceo??rg??[?0ic??[?0surgg:??[?g r? 010-62245566 13810019655
sh69p55a/k55a 5 pin descriptions pin no. 44 pin 28 pin 32 pin pad no. pin name i/o description 44 4 7 1 portg.2 /t0 /v ref i/o i i bit programmable i/o timer0 clock/counter input pin. (schmitt trigger input) external adc v ref input 1 5 8 2 portg.3 /t2 /an8 i/o i i bit programmable i/o timer2 clock/counter input pin. (schmitt trigger input) adc input channel 8 3 - 2 - - 4 - 3 portk.1 - 0 i/o bit programmable i/o 7 - 4 9 - 6 - 8 - 5 portj.3 - 0 /an7 - an4 i/o i bit programmable i/o adc input channel 7 - 4 8 10 9 10 portc.0 /pll_c i/o i p bit programmable i/o (code option) vector interrupt (active falling edge by system register setup) built-in pll connect with external capacitor 9 11 10 11 portc.1 /osco i/o i i/o bit programmable i/o (code option) vector interrupt (active falling edge by system register setup) osc output pin. no output in rc mode 10 12 11 12 portc.2 /osci i/o i i bit programmable i/o (code option) vector interrupt (active falling edge by system register setup) osc input pin, connected to a crystal, ceramic or external resistor 11 13 12 13 reset /portc.3 i i i/o reset pin input (active low, schmitt trigger input) vector interrupt (active falling edge by system register setup) bit programmable i/o, open-drain 12 14 13 9, 14, 35, 36, 43 gnd p ground pin 13 15 14 15,16 v dd p power supply pin 17 - 14 19 - 16 18 - 15 20 - 17 porta.3 - 0 /seg4 - seg1 /led_s4 - led_s1 /key_i4 - key_i1 i/o o o i bit programmable i/o seg4 - seg1 signal output for lcd display seg4 - seg1 signal output for led display input for automatic key scan 18 - 19 21 portf.0 /seg5 /led_s5 /key_i5 i/o o o i bit programmable i/o seg5 signal output for lcd display seg5 signal output for led display input for automatic key scan 21 - 19 - 22 - 20 24 - 22 portf.3 - 1 /seg8 - seg6 /led_s8 - led_s6 i/o o o bit programmable i/o seg8 - seg6 signal output for lcd display seg8 - seg6 signal output for led display 23 - 22 21 - 20 - 26- 25 porti.1 - 0 /seg10 - seg9 i/o o bit programmable i/o seg10 - seg9 signal output for lcd display 25 - 24 - - 28 - 27 porti.3 - 2 /seg12 - seg11 i/o o bit programmable i/o seg12 - seg11 signal output for lcd display 27 - 26 - - 30 - 29 porth.1 - 0 /seg14 - seg13 i/o o bit programmable i/o seg14 - seg13 signal output for lcd display 29 - 28 - 24 - 23 32 - 31 porth.3 - 2 /seg16 - seg15 i/o o bit programmable i/o seg16 - seg15 signal output for lcd display 31 - 30 23 - 22 26 - 25 34 - 33 porte.1 - 0 /com7 - com8 /seg18 - seg17 i/o o o bit programmable i/o com7 - com8 signal output for lcd display seg18 - seg17 signal output for lcd display http://www.xinpian.net ceo??rg??[?0ic??[?0surgg:??[?g r? 010-62245566 13810019655
sh69p55a/k55a 6 pin descriptions (continued) pin no. 44 pin 28 pin 32 pin pad no. pin name i/o description 33 - 32 25 - 24 28 - 27 38 - 37 porte.3 - 2 /com5 - com6 /seg20 - seg19 /led_c5 - led_c6 i/o o o o bit programmable i/o com5 - com6 signal output for lcd display seg20 - seg19 signal output for lcd display com5 - com6 signal output for led display 37 - 34 - 32 - 29 42 - 39 portd.3 - 0 /com1 - com4 /led_c1 - led_c4 /key_o1 - key_o4 i/o o o o bit programmable i/o com1 - com4 signal output for lcd display com1 - com4 signal output for led display output for automatic key scan 40 - 38 28 - 26 3 - 1 46 - 44 portb.2 - 0 /an2 - an0 i/o i i bit programmable i/o vector interrupt (active falling edge by system register setup) adc input channel 2 - 0 41 1 4 47 portb.3 /an3 i/o i i bit programmable i/o vector interrupt (active falling edge by system register setup) adc input channel 3 42 2 5 48 portg.0 /pwm i/o o bit programmable i/o pwm output 43 3 6 49 portg.1 /tone /an9 i/o o i bit programmable i/o tone generator output adc input channel 9 which, i: input; o: output; p: power; z: high impedance otp programming pin description* (otp program mode) pin no. 44 pin 28 pin 32 pin pad no. symbol i/o sharing pin description 13 15 14 14, 15 v dd pv dd programming power supply (+5.5v) 11 13 12 12 v pp p reset programming high voltage power supply (+11v) 12 14 13 13 gnd p gnd ground 10 12 11 11 sck i osci programming clock input pin 14 16 15 16 sda i/o porta.0 programming data pin *: only sh69p55a has the otp program mode, SH69K55A has not the otp program mode. http://www.xinpian.net ceo??rg??[?0ic??[?0surgg:??[?g r? 010-62245566 13810019655
sh69p55a/k55a 7 functional descriptions 1. cpu the cpu contains the followi ng functional blocks: program counter (pc), arithmetic logic unit (alu), carry flag (cy), accumulator, table branch register, data pointer (inx, dph, dpm, and dpl) and stacks. 1.1. pc the pc is used for rom addressing consisting of 12-bit: page register (pc11), and ripple carry counter (pc10, pc9, pc8, pc7, pc6, pc5, pc4, pc3, pc2, pc1, pc0). the program counter is loaded with data corresponding to each instruction. the unconditi onal jump instruction (jmp) can be set at 1-bit page register for higher than 2k. the program counter can address only 4k program rom address. (refer to the rom description). 1.2. alu and cy the alu performs arithmetic and logic operations. the alu provides the following functions: binary addition/subtraction (adc, adcm, add, addm, sbc, sbcm, sub, subm, adi, adim, sbi, sbim) decimal adjustments for addition/subtraction (daa, das) logic operations (and, andm, eor, eorm, or, orm, andim, eorim, orim) decisions (ba0, ba1, ba2, ba3, baz, bnz, bc, bnc) logic shift (shr) the carry flag (cy) holds the alu overflow that the arithmetic operation generates. during an interrupt service or call instruction, the carry fl ag is pushed into the stack and recovered from the stack by the rtni instruction. it is unaffected by the rtnw instruction. 1.3. accumulator (ac) the accumulator is a 4-bit register holding the results of the arithmetic logic unit. in conjunction with the alu, data is transferred between the accumulator and system register, or data memory can be performed. 1.4. table branch register (tbr) table data can be stored in program memory and can be referenced by using table branch (tjmp) and return constant (rtnw) instructions. the tbr and ac are placed by an offset address in program rom. tjmp instruction branch into address ((pc11 - pc8) x (2 8 ) + (tbr, ac)). the address is determined by rtnw to return look-up value into (tbr, ac). rom code bit7-bit4 is placed into tbr and bit3-bit0 into ac. 1.5. data pointer the data pointer can indirectly address data memory. pointer address is located in register dph (3-bits), dpm (3-bits) and dpl (4-bits). the addressing range is 000h--3ffh. pseudo index address (inx) is used to read or write data memory, then ram address bit9 - bit0 which comes from dph, dpm and dpl. 1.6. stack the stack is a group of regist ers used to save the contents of cy & pc (11-0) sequentially with each subroutine call or interrupt. the msb is saved for cy and it is organized into 13 bits x 8 levels. the stack is operated on a first-in, last-out basis and returned sequ entially to the pc by the return instructions (rtni/rtnw). note: the stack nesting includes both subroutine calls and interrupts requests. the maximum allowed for subroutine calls and interrupts are 8 levels. if the number of calls and interrupt requests exceeds 8, then the bottom of stack will be shifted out, that program execution may enter an abnormal state. 2. ram built-in ram contains general-purpose data memory and system register. because of its static nature, the ram can keep data after the cpu entering stop or halt. 2.1. ram addressing data memory and system register can be accessed in one inst ruction by direct addressing. the following is the memory allocation map: system register: $000 - $02f, $380 - $3af, $3c0 - $3c2 data memory: $030 - $1a7 lcd ram space: $300 - $313, $320 - $333 ram bank table: bank 0 b = 0 bank 1 b = 1 bank 2 b = 2 bank 3 b = 3 bank 4 b = 4 bank 5 b = 5 bank 6 b = 6 bank 7 b = 7 $000 - $07f $080 - $0ff $100 - $17f $180 - $1ff $200 - $27f $280 - $2ff $300 - $37f $380 - $3af, $3c0 - $3c2 where, b: ram bank bit use in instructions http://www.xinpian.net ceo??rg??[?0ic??[?0surgg:??[?g r? 010-62245566 13810019655
sh69p55a/k55a 8 2.2. configuration of system register: address bit 3 bit 2 bit 1 bit 0 r/w remarks $00 iet0 iet1 iet2 ieex r/w int errupt enable flags register $01 irqt0 irqt1 irqt2 irqex r/w interrupt request flags register $02 t0s t0m.2 t0m.1 t0m.0 r/w bit2-0: timer0 mode register bit3: t0 signal source select register $03 t0e t1m.2 t1m.1 t1m.0 r/w bit2-0: timer1 mode register bit3: t0 signal edge select register $04 t0l.3 t0l.2 t0l.1 t0l.0 r/w timer0 load/counter low nibble register $05 t0h.3 t0h.2 t0h.1 t0h.0 r/w timer0 load/counter high nibble register $06 t1l.3 t1l.2 t1l.1 t1l.0 r/w timer1 load/counter low nibble register $07 t1h.3 t1h.2 t1h.1 t1h.0 r/w timer1 load/counter high nibble register $08 pa.3 pa.2 pa.1 pa.0 r/w porta data register $09 pb.3 pb.2 pb.1 pb.0 r/w p ortb data register $0a pc.3 pc.2 pc.1 pc.0 r/w portc data register $0b pd.3 pd.2 pd.1 pd.0 r/w portd data register $0c pe.3 pe.2 pe.1 pe.0 r/ w porte data register $0d pf.3 pf.2 pf.1 pf.0 r/w portf data register $0e tbr.3 tbr.2 tbr.1 tbr. 0 r/w table branch register $0f inx.3 inx.2 inx.1 inx.0 r/w pseudo index register $10 dpl.3 dpl.2 dpl.1 dpl.0 r/w data poi nter for inx low nibble register $11 - dpm.2 dpm.1 dpm.0 r/w data point er for inx middle nibble register $12 - dph.2 dph.1 dph.0 r/w data pointer for inx high nibble register $13 v ref acr2 acr1 acr0 r/w bit2-0: a/d port configuration control register bit3: select internal/external reference voltage register $14 adcon ch2 ch1 ch0 r/w bit2-0: adc channel control register bit3: adc module operate control register $15 t2e t2sc.2 t2sc.1 t2sc.0 r/w bit2-0: timer2 pre-scaler register bit3: t2 external signal edge select register $16 fs1 fs0 oxs oxon r/w bit0: turn on pll register bit1: clock source select (1: pll, 0: 32.768khz) register bit3-2: pll frequency select register $17 lvr - - - r/w bit3: low voltage reset flag register (read and write 0 only) $18 pacr.3 pacr.2 pacr.1 pacr.0 r/w port a input/output control register $19 pbcr.3 pbcr.2 pbcr.1 pbcr.0 r/w port b input/output control register $1a pccr.3 pccr.2 pccr.1 pccr.0 r/w portc input/out put control register $1b pdcr.3 pdcr.2 pdcr.1 pdcr.0 r/w portd input/out put control register $1c pecr.3 pecr.2 pecr.1 pecr.0 r/w port e input/output control register $1d pfcr.3 pfcr.2 pf cr.1 pfcr.0 r/w portf input/o utput control register $1e wdt wdt.2 wdt.1 wdt.0 r/w r bit2-0: watch dog timer control register bit3: watchdog timer overflow flag register (read only) $1f - - bnk1 bnk0 r/w bit1-0: rom bank register http://www.xinpian.net ceo??rg??[?0ic??[?0surgg:??[?g r? 010-62245566 13810019655
sh69p55a/k55a 9 configuration of system register (continued1): address bit 3 bit 2 bit 1 bit 0 r/w remarks $20 pwms tck1 tck0 pwm_en r/w bit0: pwm output enable control register bit2-1: pwm clock control register bit3: pwm output mode of duty cycle control register $21 pp.3 pp.2 pp.1 pp.0 r/w pwm period low nibble register $22 pp.7 pp.6 pp.5 pp.4 r/w pwm period high nibble register $23 - fstp - - r/w bit2: 32.768khz oscillator is closed in the stop $24 - - pdf.1 pdf.0 r/w pwm duty fine-tune bits register (2 bits) $25 pd.3 pd.2 pd.1 pd.0 r/w pwm duty low nibble register (4 bits) $26 pd.7 pd.6 pd.5 pd.4 r/w pwm duty high nibble register (4bits) $27 t2go dec tm2s1 tm2s0 r/w bit1-0: timer2 mode select register bit2: select directive edge active enable register bit3: set timer2 function start register $28 keynum1 keynum0 keyend keyen r/w r bit0: key scan enable register bit1: key scan end/processing register bit3-2: key scan result register $29 lcdon duty2 duty1 duty0 r/w bit2-0: set duty and com register bit3: lcd display on control register $2a - - - - r/w reserved $2b leden ledon eduty1 eduty0 r/w bit1-0: set duty register bit2: turn on led driver register bit3: enable led driver register $2c keyc3 keyc2 keyc1 keyc0 r bit3-0: the result of key scan on key_o4 - 1 register $2d keyl3 keyl2 keyl1 keyl0 r bit3-0: the result of key scan on key_i5 - 1 register $2e rlcd ps2 ps1 ps0 r/w bit2-0: configuration the segment register bit3: lcd bias resistor set register $2f go/ done tadc1 tadc0 - r/w bit2-1: a/d conversion time control register bit3: adc startup/status flag register $380 rdt.3 rdt.2 rdt.1 rdt.0 r/w rom data table address/data register $381 rdt.7 rdt.6 rdt.5 rdt.4 r/w rom data table address/data register $382 rdt.11 rdt.10 rdt.9 rdt.8 r/w rom data table address/data register $383 rdt.15 rdt.14 rdt.13 rdt.12 r/w rom data table address/data register $384 t2d.3 t2d.2 t2d.1 t2d. 0 r/w timer2 load/counter low nibble register $385 t2d.7 t2d.6 t2d.5 t2d. 4 r/w timer2 load/counter middle_l nibble register $386 t2d.11 t2d.10 t2d.9 t2 d.8 r/w timer2 load/counter middle_h nibble register $387 t2d.15 t2d.14 t2d.13 t2d. 12 r/w timer2 load/counter high nibble register $388 pbien.3 pbien.2 pbien.1 pbien.0 r/w p ortb interrupt enable flags register $389 pbif.3 pbif.2 pbgif.1 pbif.0 r/w por tb interrupt request flags register $38a pcien.3 pcien.2 pcien.1 pcien.0 r/w portc interrupt enable flags register $38b pcif.3 pcif.2 pcif.1 pcif.0 r/w p ortc interrupt request flags register $38c - - keyie adie r/w bit0: ad interrupt enable flag register bit1: key scan interrupt enable flag register $38d - - keyif adif r/w bit0: ad interrupt request flag register bit1: key scan interrupt request flag register $38e pg.3 pg.2 pg.1 pg.0 r/w portg data register $38f ph.3 ph.2 ph.1 ph.0 r/w porth data register http://www.xinpian.net ceo??rg??[?0ic??[?0surgg:??[?g r? 010-62245566 13810019655
sh69p55a/k55a 10 configuration of system register (continued2): address bit 3 bit 2 bit 1 bit 0 r/w remarks $390 pi.3 pi.2 pi.1 pi.0 r/w porti data register $391 pj.3 pj.2 pj.1 pj.0 r/w portj data register $392 - - pk.1 pk.0 r/w portk data register $393 pgcr.3 pgcr.2 pg cr.1 pgcr.0 r/w portg input/o utput control register $394 phcr.3 phcr.2 phcr.1 phcr.0 r/w porth input/out put control register $395 picr.3 picr.2 pi cr.1 picr.0 r/w porti input/o utput control register $396 pjcr.3 pjcr.2 pjcr.1 pjcr.0 r/w port j input/output control register $397 - - pkcr.1 pkcr.0 r/w portk i nput/output control register $398 ppacr.3 ppacr.2 ppacr.1 ppacr.0 r/w porta pull high control register $399 ppbcr.3 ppbcr.2 ppbcr.1 ppbcr.0 r/w port b pull high control register $39a - ppccr.2 ppccr.1 ppccr.0 r/w portc pull high control register $39b ppdcr.3 ppdcr.2 ppdcr.1 ppdcr.0 r/w port d pull high control register $39c ppecr.3 ppecr.2 ppecr.1 ppecr.0 r/w port e pull high control register $39d ppfcr.3 ppfcr.2 ppfcr.1 ppf cr.0 r/w portf pull high control register $39e ppgcr.3 ppgcr.2 ppgcr.1 ppg cr.0 r/w portg pull high control register $39f pphcr.3 pphcr.2 pphcr.1 pphcr.0 r/w port h pull high control register $3a0 ppicr.3 ppicr.2 ppicr.1 ppi cr.0 r/w porti pull high control register $3a1 ppjcr.3 ppjcr.2 ppjcr.1 ppjcr.0 r/w port j pull high control register $3a2 - - ppkcr.1 ppkcr.0 r/w portk pull high control register $3a3 tg1.3 tg1.2 tg1.1 tg1.0 r/w tone generator 1 low nibble register $3a4 tg1.7 tg1.6 tg1.5 tg 1.4 r/w tone generator 1 middle nibble register $3a5 tg1.11 tg1.10 tg1.9 tg1.8 r/w t one generator 1 high nibble register $3a6 tg2.3 tg2.2 tg2.1 tg2.0 r/w tone generator 2 low nibble register $3a7 tg2.7 tg2.6 tg2.5 tg 2.4 r/w tone generator 2 middle nibble register $3a8 tg2.11 tg2.10 tg2.9 tg2.8 r/w t one generator 2 high nibble register $3a9 tv1.3 tv1.2 tv1.1 tv1.0 r/w tone generator 1 volume low nibble register $3aa tg1en tv1.6 tv1.5 tv1.4 r/w bit2-0: tone generator 1 volume high nibble register bit3: tone generator 1 enable register $3ab tv2.3 tv2.2 tv2.1 tv2.0 r/w tone generator 2 volume low nibble register $3ac tg2en tv2.6 tv2.5 tv2.4 r/w bit2-0: tone generator 2 volume high nibble register bit3: tone generator 2 enable register $3ad - - a1 a0 r adc data low nibble register $3ae a5 a4 a3 a2 r adc data middle nibble register $3af a9 a8 a7 a6 r adc data high nibble register $3c0 t1s - - - r/w t1 signal source select register $3c1 lps3 lps2 lps1 lps0 r/w bit3-0: lcd frame frequency control register $3c2 acr3 ch3 - - r/w bit3: a/d port configuration control register bit2: adc channel control register http://www.xinpian.net ceo??rg??[?0ic??[?0surgg:??[?g r? 010-62245566 13810019655
sh69p55a/k55a 11 3. rom the rom can address 8192 x 16 bits of program area from $000 to $1fff. 3.1. vector address area ($000 to $004) the program is sequentially executed. t here is an area address $000 through $004 that is reserved for a special interrupt service routine such as starting vector address. address instruction remarks $000 jmp* jump to reset service routine $001 jmp* jump to timer0 interrupt service routine $002 jmp* jump to timer1 interrupt service routine $003 jmp* jump to timer2 interrupt service routine $004 jmp* jump to external interrupts service routine * jmp instruction can be r eplaced by any instruction. 3.2. bank switch mapping program counter (pc11 - pc0) can only address 4k rom spac e. the bank switch technique is used to extend the cpu address space. the lower 2k of the cpu address space maps to the lower 2k of rom space (bank0). the upper 2k of the cpu address space maps to one of the three banks (b nk3-0 = 0, 1, 2) of the upper 6k of rom. the bank switch mapping is as follows: rom space cpu address bnk = $00 bnk = $01 bnk = $02 low 2k address 0000 - 07ff (bank 0) 0000 - 07ff (bank 0) 0000 - 07ff (bank 0) upper 2k address 0800 - 0fff (bank 1) 1000 - 17ff (bank 2) 1800 - 1fff (bank 3) http://www.xinpian.net ceo??rg??[?0ic??[?0surgg:??[?g r? 010-62245566 13810019655
sh69p55a/k55a 12 4. initial state 4.1. system register state: address bit 3 bit 2 bit 1 bit 0 power on reset /pin reset wdt reset /low voltage reset $00 iet0 iet1 iet2 ieex 0000 0000 $01 irqt0 irqt1 irqt2 irqex 0000 0000 $02 t0s t0m.2 t0m.1 t0m.0 0000 uuuu $03 t0e t1m.2 t1m.1 t1m.0 0000 uuuu $04 t0l.3 t0l.2 t0l.1 t0l.0 xxxx xxxx $05 t0h.3 t0h.2 t0h.1 t0h.0 xxxx xxxx $06 t1l.3 t1l.2 t1l.1 t1l.0 xxxx xxxx $07 t1h.3 t1h.2 t1h.1 t1h.0 xxxx xxxx $08 pa.3 pa.2 pa.1 pa.0 0000 0000 $09 pb.3 pb.2 pb.1 pb.0 0000 0000 $0a pc.3 pc.2 pc.1 pc.0 0000 0000 $0b pd.3 pd.2 pd.1 pd.0 0000 0000 $0c pe.3 pe.2 pe.1 pe.0 0000 0000 $0d pf.3 pf.2 pf.1 pf.0 0000 0000 $0e tbr.3 tbr.2 tb r.1 tbr.0 xxxx uuuu $0f inx.3 inx.2 inx.1 inx.0 xxxx uuuu $10 dpl.3 dpl.2 dpl. 1 dpl.0 xxxx uuuu $11 - dpm.2 dpm.1 dpm.0 -xxx -uuu $12 - dph.2 dph.1 dph.0 -xxx -uuu $13 v ref acr2 acr1 acr0 0000 uuuu $14 adcon ch2 ch1 ch0 0000 0uuu $15 t2e t2sc.2 t2sc.1 t2sc.0 0000 uuuu $16 fs1 fs0 oxs oxon 0000 uuuu $17 lvr - - - 0--- *--- $18 pacr.3 pacr.2 pacr.1 pacr.0 0000 0000 $19 pbcr.3 pbcr.2 pbcr. 1 pbcr.0 0000 0000 $1a pccr.3 pccr.2 p ccr.1 pccr.0 0000 0000 $1b pdcr.3 pdcr.2 p dcr.1 pdcr.0 0000 0000 $1c pecr.3 pecr.2 pe cr.1 pecr.0 0000 0000 $1d pfcr.3 pfcr.2 pfcr.1 pfcr.0 0000 0000 $1e wdt wdt.2 wdt.1 wdt.0 0000 #000 $1f - - bnk1 bnk0 --00 --00 $20 pwms tck1 tck0 pwm_en 0000 uuu0 $21 pp.3 pp.2 pp.1 pp.0 xxxx uuuu $22 pp.7 pp.6 pp.5 pp.4 xxxx uuuu $23 - fstp -0-- -0-- http://www.xinpian.net ceo??rg??[?0ic??[?0surgg:??[?g r? 010-62245566 13810019655
sh69p55a/k55a 13 system register state (continued1): address bit 3 bit 2 bit 1 bit 0 power on reset /pin reset wdt reset /low voltage reset $24 pdf.1 pdf.0 --xx --uu $25 pd.3 pd.2 pd.1 pd.0 xxxx uuuu $26 pd.7 pd.6 pd.5 pd.4 xxxx uuuu $27 t2go dec tm2s1 tm2s0 0000 0uuu $28 keynum1 keynum0 keyend keyen 0000 000u $29 lcdon duty2 duty1 duty0 0000 uuuu $2a - - - - ---- ---- $2b leden ledon eduty1 eduty0 0000 uuuu $2c keyc3 keyc2 keyc1 keyc0 0000 uuuu $2d keyl3 keyl2 keyl1 keyl0 0000 uuuu $2e rlcd ps2 ps1 ps0 0000 uuuu $2f go/ done tadc1 tadc0 - 000- 0uu- $380 rdt.3 rdt.2 rdt.1 rdt.0 xxxx uuuu $381 rdt.7 rdt.6 rdt.5 rdt.4 xxxx uuuu $382 rdt.11 rdt.10 rdt.9 rdt.8 xxxx uuuu $383 rdt.15 rdt.14 rdt .13 rdt.12 xxxx uuuu $384 t2d.3 t2d.2 t2d.1 t2d.0 xxxx xxxx $385 t2d.7 t2d.6 t2d.5 t2d.4 xxxx xxxx $386 t2d.11 t2d.10 t2d.9 t2d.8 xxxx xxxx $387 t2d.15 t2d.14 t2d.13 t2d.12 xxxx xxxx $388 pbien.3 pbien.2 pbi en.1 pbien.0 0000 0000 $389 pbif.3 pbif.2 pbif.1 pbif.0 0000 0000 $38a pcien.3 pcien.2 pcien.1 pcien.0 0000 0000 $38b pcif.3 pcif.2 pcif.1 pcif.0 0000 0000 $38c - keyie adie --00 --00 $38d - - keyif adif --00 --00 $38e pg.3 pg.2 pg.1 pg.0 0000 0000 $38f ph.3 ph.2 ph.1 ph.0 0000 0000 $390 pi.3 pi.2 pi.1 pi.0 0000 0000 $391 pj.3 pj.2 pj.1 pj.0 0000 0000 $392 - - pk.1 pk.0 --00 --00 $393 pgcr.3 pgcr.2 pg cr.1 pgcr.0 0000 0000 $394 phcr.3 phcr.2 p hcr.1 phcr.0 0000 0000 $395 picr.3 picr.2 pi cr.1 picr.0 0000 0000 $396 pjcr.3 pjcr.2 pj cr.1 pjcr.0 0000 0000 $397 - - pkcr.1 pkcr.0 --00 --00 $398 ppacr.3 ppacr.2 pp acr.1 ppacr.0 0000 0000 http://www.xinpian.net ceo??rg??[?0ic??[?0surgg:??[?g r? 010-62245566 13810019655
sh69p55a/k55a 14 system register state (continued2): address bit 3 bit 2 bit 1 bit 0 power on reset /pin reset wdt reset /low voltage reset $399 ppbcr.3 ppbcr.2 ppb cr.1 ppbcr.0 0000 0000 $39a - ppccr.2 ppccr.1 ppccr.0 -000 -000 $39b ppdcr.3 ppdcr.2 pp dcr.1 ppdcr.0 0000 0000 $39c ppecr.3 ppecr.2 ppecr.1 ppecr.0 0000 0000 $39d ppfcr.3 ppfcr.2 ppfcr.1 ppfcr.0 0000 0000 $39e ppgcr.3 ppgcr.2 ppg cr.1 ppgcr.0 0000 0000 $39f pphcr.3 pphcr.2 pp hcr.1 pphcr.0 0000 0000 $3a0 ppicr.3 ppicr.2 ppi cr.1 ppicr.0 0000 0000 $3a1 ppjcr.3 ppjcr.2 ppj cr.1 ppjcr.0 0000 0000 $3a2 - - ppkcr.1 ppkcr.0 --00 --00 $3a3 tg1.3 tg1.2 tg 1.1 tg1.0 xxxx uuuu $3a4 tg1.7 tg1.6 tg 1.5 tg1.4 xxxx uuuu $3a5 tg1.11 tg1.10 tg 1.9 tg1.8 xxxx uuuu $3a6 tg2.3 tg2.2 tg 2.1 tg2.0 xxxx uuuu $3a7 tg2.7 tg2.6 tg 2.5 tg2.4 xxxx uuuu $3a8 tg2.11 tg2.10 tg 2.9 tg2.8 xxxx uuuu $3a9 tv1.3 tv1.2 tv 1.1 tv1.0 xxxx uuuu $3aa tg1en tv1.6 tv1.5 tv1.4 xxxx uuuu $3ab tv2.3 tv2.2 tv2.1 tv2.0 xxxx uuuu $3ac tg2en tv2.6 tv 2.5 tv2.4 xxxx uuuu $3ad - - a1 a0 --xx --uu $3ae a5 a4 a3 a2 xxxx uuuu $3af a9 a8 a7 a6 xxxx uuuu $3c0 t1s - - - 0--- u--- $3c1 lps3 lps2 lps1 lps0 0000 uuuu $3c2 acr3 ch3 - - 00-- uu-- legend: x = unknown; u = unchanged; - = unimplemented read as '0'. *, #: for the detail information, refer to the following table: wdt reset lvr reset wdt reset & lvr reset power on reset/pin reset * 0 1 1 0 # 1 0 1 0 4.2. others initial state: others after any reset program counter (pc) $000 cy undefined accumulator (ac) undefined data memory undefined http://www.xinpian.net ceo??rg??[?0ic??[?0surgg:??[?g r? 010-62245566 13810019655
sh69p55a/k55a 15 5. system clock and oscillator sh69p55a/69k55a has one clock source, which is determined in code options. the oscillator generates the basic clock pulses that provide the system clock to supply cpu and on-chip peripherals. system clock f sys = f osc /4. 5.1. instruction cycle time: (1) 4/32.768khz ( 122 s) for 32.768khz oscillator. (2) 4/8mhz (= 0.5 s) for 8 mhz oscillator. 5.2. oscillator type (1) crystal oscillator: 32.768khz or 400khz - 8mhz osci osco c1 c2 crystal pll_c (2) ceramic resonator: 400khz - 8mhz osci osco c1 c2 ceramic pll_c (3) rc oscillator: 400khz - 8mhz osci rosc v dd osco pll_c external rc (4) rc oscillator: 4mhz osci osco pll_c internal rc (5) pll oscillator (1, 2, 4, 8mhz) osci osco c1 c2 32.768 khz pll_c c3 = 2200p r pll = 100k note: - if the external rc osc illator is selected, osco pin is used as the i/o port (portc.1). - if the internal rc oscillator is selected, osco pin is used as the i/o port (portc.1) and osci pin is used as the i/o port (portc.2). - if the pll is disabled, pll_c is used as the i/o port (portc.0). http://www.xinpian.net ceo??rg??[?0ic??[?0surgg:??[?g r? 010-62245566 13810019655
sh69p55a/k55a 16 5.3. control of phase locked loop clock source (pll) a phase locked loop (pll) is built in sh69p55a/69k55a, whic h can provide up to 8mhz cl ock source when the 32.768khz oscillator is selected. pll control regi ster can decide whether pll enable or di sable. when pll is enabled, portc.0 is shared as pll capacitor connecting port, which is connected with a rc network. when pll is disabled, portc.0 is shared as a normal i/o. pll control register $16 address bit 3 bit 2 bit 1 bit 0 r/w remarks $16 fs1 fs0 oxs oxon r/w bit0: turn on pll register bit1: clock source select (1: pll, 0: 32.768khz) register bit3 - 2: pll frequency select register x x x 0 r/w turn off pll x x x 1 r/w turn on pll, when 32.768khz oscillator is selected in code option x x 0 x r/w clock source is se lected as 32.768khz oscillator x x 1 1 r/w clock source is selected as pll 0 0 1 1 r/w pll provides 8.126mhz clock signal for clock source (lvr voltage range must be selected as 4v in the code option) 0 1 1 1 r/w pll provides 4.063mhz clock signal for clock source 1 0 1 1 r/w pll provides 2.031mhz clock signal for clock source 1 1 1 1 r/w pll provides 1.016mhz clock signal for clock source note: 1. usage of pll: first, configure the fs1 and fs0 in pll control register. second, set oxon = 1 and turn on the pll. third, wait at least 2ms. last, set oxs = 1 and select pll as the system clock source. 2. if lvr voltage range is selected as 2.5v in the code option, the pll only provides 1, 2, 4mhz clock signal for clock source. system register $23 address bit 3 bit 2 bit 1 bit 0 r/w remarks $23 - fstp - - r/w bit2: 32.768khz oscillator is closed in the stop x 1 x x r/w 32.768khz oscillator is closed in the stop, if 32.768khz is selected in the code option x 0 x x r/w 32.768khz oscillator is not closed in the stop, if 32.768khz oscillator is selected in the code option http://www.xinpian.net ceo??rg??[?0ic??[?0surgg:??[?g r? 010-62245566 13810019655
sh69p55a/k55a 17 5.4. capacitor sel ection for oscillator ceramic resonators frequency c1 c2 recommend type manufacturer ztb 455khz vectron international 455khz 47 - 100pf 47 - 100pf zt 455e shenzhen dgjb electronic co.,ltd. ztt 3.580m vectron international 3.58mhz - - zt 3.58m* shenzhen dgjb electronic co.,ltd. ztt 4.000m vectron international 4mhz - - zt 4m* shenzhen dgjb electronic co.,ltd. *- the specified ceramic resonator has internal built-in load capacity crystal oscillator frequency c1 c2 recommend type manufacturer dt 38 ( 3x8) kds 32.768khz 5 - 12.5pf 5 - 12.5pf 3x8 - 32.768khz vectron international hc-49u/s 4.000mhz vectron international 4mhz 8 - 15pf 8 - 15pf 49s-4.000m-f16e shenzhen dgjb electronic co.,ltd. hc-49u/s 8.000mhz vectron international 8mhz 8 - 15pf 8 - 15pf 49s-8.000m-f16e shenzhen dgjb electronic co.,ltd. notes: 1. capacitor values are used for design guidance only! 2. these capacitors were tested with the crys tals listed above for basic start-up and operation. they are not optimized. 3. be careful for the stray capacitance on pcb board, the user should test the performance of t he oscillator over the expected v dd and the temperature range for the application. before selecting crystal/ceramic, the us er should consult the crystal/ceramic manuf acturer for appropriate value of external component to get best performance, visit http://www.sinowealth.com for more recommended manufactures http://www.xinpian.net ceo??rg??[?0ic??[?0surgg:??[?g r? 010-62245566 13810019655
sh69p55a/k55a 18 6. i/o port the sh69p55a/69k55a provides 42 bi-directional i/o ports including one open-drain outpu t. the port data is put in register $08 - $0d and $38e - $392. the port control register ($18 - $1 d and $393 - $397) controls the port as input or output. each i/o port (excluding those open drain output ports) contains pull-high resistor, which is c ontrolled by the value of the corresponding bit in the port pull-high control register ($398 - $3a2), independently. ? when the port is selected as an input port, write ?1? to the re levant bit in the port pull-hi gh control register ($398 - $3a2) could turn on the pull high resistor and write ?0? could turn off the pull high resistor. ? when the port is selected as output por t, the pull high resistor will be turned off automatically, regardless the value of the corresponding bit in the port pull high control register ($398 - $3a2). ? when portb and portc are selected as the digital input direct ion, they can active port interrupt by falling edge (if port interrupt is enabled). system register $08 - $0d, $38e - $392: port data register (pdr) address bit3 bit2 bit1 bit0 r/w remarks $08 pa.3 pa.2 pa.1 pa.0 r/w porta data register $09 pb.3 pb.2 pb.1 pb.0 r/w p ortb data register $0a pc.3 pc.2 pc.1 pc.0 r/w portc data register $0b pd.3 pd.2 pd.1 pd.0 r/w portd data register $0c pe.3 pe.2 pe.1 pe.0 r/ w porte data register $0d pf.3 pf.2 pf.1 pf.0 r/w portf data register $38e pg.3 pg.2 pg.1 pg.0 r/w portg data register $38f ph.3 ph.2 ph.1 ph.0 r/w porth data register $390 pi.3 pi.2 pi.1 pi.0 r/w porti data register $391 pj.3 pj.2 pj.1 pj.0 r/w portj data register $392 - - pk.1 pk.0 r/w portk data register system register $18 - $1d, $393 - $397 : port control register (pcr) address bit3 bit2 bit1 bit0 r/w remarks $18 pacr.3 pacr.2 pacr.1 pacr.0 r/w port a input/output control register $19 pbcr.3 pbcr.2 pbcr.1 pbcr.0 r/w port b input/output control register $1a pccr.3 pccr.2 pccr.1 pccr.0 r/w portc input/out put control register $1b pdcr.3 pdcr.2 pdcr.1 pdcr.0 r/w portd input/out put control register $1c pecr.3 pecr.2 pecr.1 pecr.0 r/w port e input/output control register $1d pfcr.3 pfcr.2 pf cr.1 pfcr.0 r/w portf input/o utput control register $393 pgcr.3 pgcr.2 pg cr.1 pgcr.0 r/w portg input/o utput control register $394 phcr.3 phcr.2 phcr.1 phcr.0 r/w porth input/out put control register $395 picr.3 picr.2 pi cr.1 picr.0 r/w porti input/o utput control register $396 pjcr.3 pjcr.2 pjcr.1 pjcr.0 r/w port j input/output control register $397 - - pkcr.1 pkcr.0 r/w portk i nput/output control register pa (/b/c/d/e/f/g/h/i/j) pcr.n, (n = 0, 1, 2, 3), pkpcr.n (n = 0, 1) 0: set i/o as an input direction. (power on initial) 1: set i/o as an output direction. http://www.xinpian.net ceo??rg??[?0ic??[?0surgg:??[?g r? 010-62245566 13810019655
sh69p55a/k55a 19 system register $398 - $3a2: port pull-high control register (ppcr) address bit3 bit2 bit1 bit0 r/w remarks $398 ppacr.3 ppacr.2 ppa cr.1 ppacr.0 r/w porta pull high control register $399 ppbcr.3 ppbcr.2 ppbcr.1 ppbcr.0 r/w po rtb pull high control register $39a - ppccr.2 ppccr.1 ppccr.0 r/w port c pull high control register $39b ppdcr.3 ppdcr.2 ppdcr.1 ppdcr.0 r/w po rtd pull high control register $39c ppecr.3 ppecr.2 ppecr.1 ppecr.0 r/w po rte pull high control register $39d ppfcr.3 ppfcr.2 ppfcr.1 ppfcr.0 r/w po rtf pull high control register $39e ppgcr.3 ppgcr.2 ppgcr.1 ppgcr.0 r/w portg pull hi gh control register $39f pphcr.3 pphcr.2 pphcr.1 pphcr.0 r/w po rth pull high control register $3a0 ppicr.3 ppicr.2 ppicr.1 ppicr.0 r/w porti pull high control register $3a1 ppjcr.3 ppjcr.2 ppjcr.1 ppjcr.0 r/w po rtj pull high control register $3a2 - - ppkcr.1 ppkcr.0 r/w portk pull high control register pa (/b/d/e/f/g/h/i/j) cr.n, (n = 0, 1, 2, 3) , pkcr.n (n = 0, 1), pccr.n (n = 0, 1, 2) 0: disable internal pull-high resistor. (power on initial) 1: enable internal pull-high resistor. equivalent circuit for a single i/o pin i/o control register data register pull high register m2t1 0 1 s read data in data read i/o pad pull high v dd gnd v dd http://www.xinpian.net ceo??rg??[?0ic??[?0surgg:??[?g r? 010-62245566 13810019655
sh69p55a/k55a 20 porta.3 - 0 can be shared with seg4 - seg1 signal output for lcd or led display, key_i4 - key_i1 input for automatic key scan. portb.3 - 0 can be shared with adc an3 - 0 input channel. portc.0 can be shared with pll_c (code option), if pll is enab led, a rc network must be connected with this port. the osco pin can be shared with portc.1 if the sh69p55a/69k 55a uses the external clock or the rc oscillator as the system oscillation. the osci pin can be shared with portc.2, if the sh69p55a/69k55a uses the internal rc oscillator as the system oscillation. the reset pin can be shared with portc.3 controll ed by the code option. portc.3 is open-drain output. portd.3 - 0 can be shared with com1 - com4 signal output for lcd or led display, key_o1 - key_o4 output for automatic key scan. porte.3 - 0 can be shared with com5 - com8 or seg20 - seg17 signal output for lcd display, and porte.3 - 2 can be shared with com5 - 6 signal output for led display. portf.3 - 0 can be shared with seg8 - seg5 signal output for lcd or led display, and portf0 can be shared with key_i5 input for automatic key scan. portg.0 can be shared with pwm output. portg.1 can be shared with tone output or adc an9. portg.2 can be shared with t0 input or external adc v ref input. portg.3 can be shared with t2 input or adc an8. porth.3 - 0 can be shared with seg16 - seg13 signal output for lcd display. porti.3 - 0 can be shared with seg12 - seg9 signal output for lcd display. portj.3 - 0 can be shared with adc an7 - 4 input channels. important: ? in 32pin package, porth.0, porth.1 and porti - k must be selected to be output ?0? (port control register (pcr): $394 = xx11b, $395 - $396 = 1111b, $397 = 0011b and port data register (pdr): $38f = xx00b and $390 - $391 = 0000b, $392 = 0000b). ? in 28pin package, portd, portf, porth, porti.3 - 2 and portk must be selected to be output ?0? (port control register (pcr): $1b $1d, $394 = 1111b, $395 = 11xxb, $397 = 0011b and port data register (pdr): $0b $0d, $38f = 0000b, $390 = 00xxb, $392 = 0000b). ? in sh69p55a/69k55a, each output port contains a latch, which can hold the output data. writing the port data register (pdr) under the output mode can directly transfers data to the corresponding pin. all input ports do not have latches, so the external input data should be held externally until the i nput data is get from outside. the contents of the port control register (pcr) determines each bi-directional i/o port to be an input or output port, where writing ?0? to port control registe r (pcr) represents the input mode and ?1? for the output mode. when a digital i/o port is selected to be an output port, the value of the associated port bit actually represents the value of the output data latch, not the voltage on the pin. when a digital i/o port is selected to be input, the value of the asso ciated port bit represents the status on the corresponding pin. the output data latch can be written all the while, regardless of the state of the port control register (pcr). therefore, when using ports in a mixture of input and output modes, the contents of the output latches for those ports that are selected as inputs may be rewritten by execution of logical instructions. so it is strongly recommended that writing proper data to the port data register (pdr) before changing the corresponding bits in the port control register (pcr) from the input mode to the output mode can avoid glitches on the relevant pins. http://www.xinpian.net ceo??rg??[?0ic??[?0surgg:??[?g r? 010-62245566 13810019655
sh69p55a/k55a 21 ? port interrupt the portb and portc are used as port interrupt sources. since portb and portc are bit programmable i/os, only when the portb and portc are selected as normal i/o input, the voltage transition from v dd to gnd applying to the digital input port can generate a port interrupt. when they are selected as analog input (such as adc input), port interrupt request cannot be generated. the interrupt control flags are mapped on $388 - $38a of the system register. they can be accessed by the read/write operation. those flags are clear to ?0? at the initialization by the chip reset. port interrupts can be used to wake up the cpu from the halt or the stop mode. system register $388, $38a: port interrupt enable flags register address bit 3 bit 2 bit 1 bit 0 r/w remarks $388 pbien.3 pbien.2 pbien.1 pbien.0 r/w portb interrupt enable flags register $38a pcien.3 pcien.2 pcien.1 pcien.0 r/w portc interrupt enable flags register pb/cien.n, (n = 0, 1, 2, 3) 0: disable port interrupt. (power on initial) 1: enable port interrupt. system register $389, $38b : port interrupt request flags register address bit 3 bit 2 bit 1 bit 0 r/w remarks $389 pbif.3 pbif.2 pbif.1 pbif.0 r/w portb interrupt request flags register $38b pcif.3 pcif.2 pcif.1 pcif.0 r/w portc interrupt request flags register pb/cif.n, (n = 0, 1, 2, 3) 0: port interrupt is not presented. (power on initial) 1: port interrupt is presented. only writing these bits to ?0? is available. following is the port interrupt function block-diagram for reference. irqex interrupt cpu ieex external interrupt request generator pc.3 - 0 request flag (pcif.3 - 0) pccr.3 - 0 falling edge detector pbien.3 - 0 pb.3 - 0 request flag (pbif.3 - 0) pbcr.3 - 0 falling edge detector pcien.3 - 0 port interrupt programming notes: ? any one of portb & portc input pin transitions from v dd to gnd would set pbif.x or pcif.x to ?1?, in spite of level of the other pin of portb and portc. ? if pbien.x (or pcien.x) = 1and ieex = 1, the x of portb (or portc) input pin transitions from v dd to gnd would generate an interrupt request (pbif.x = 1 or pcif.x = 1) and inte rrupt the cpu, in spite of level of the other pin of portb (or portc). http://www.xinpian.net ceo??rg??[?0ic??[?0surgg:??[?g r? 010-62245566 13810019655
sh69p55a/k55a 22 7. timer sh69p55a/69k55a has three timers: two 8-bit timers (timer0, timer1) and one 16-bit timer (timer2). the 8-bit timer/counter has the following features: - 8-bit up-counting timer/counter. - automatic re-load counter. - 8-level prescaler. - interrupt on overflow from $ff to $00. the following is a simplified timer0/timer1 block diagram. prescaler system clock t osc sync 8-bit counter tm.2 tm.0 tm.1 eor t0e t0s t0 mux the timer0/timer1 provides the following functions: - programmable interval timer function. - read counter value. 7.1. timer0 and timer1 configuration and operation both the timer0 and timer1 consist of an 8-bit write-only timer load register (tl0l, tl0h; tl1l, tl1h) and an 8-bit read-only timer counter (tc0l, tc0h; tc1l, tc1h). each of them has low-order digits and high-order digits. writing data into the timer load register (tl0l, tl0h; tl1l, tl1h) can initialize the timer counter. the low-order digit should be written first, and then the high-order digit. the timer/counter is automatically loaded with the contents of the load register when the high order digit is written or the counter counts overflow from $ff to $00. timer load register: since the register h controls the physical read and write operations. please follow these steps: write operation: low nibble first high nibble to update the counter read operation: high nibble first low nibble followed. load reg. h 8-bit timer counter load reg. l latch reg. l 7.2. timer0 and timer1 mode register the timer can be programmed in several different prescalers by setting timer mode register (t0m, t1m). the clock source pre-scale by the 8-level counter first, t hen generate the output plus to timer counter. the timer mode registers (t0m, t1m) are 3-bit registers used for t he timer control as shown in table 1 and table 2. table 1. timer0 mode register ($02) t0m.2 t0m.1 t0m.0 prescaler divide ratio clock source 0 0 0 /2 11 system clock/t0 0 0 1 /2 9 system clock/t0 0 1 0 /2 7 system clock/t0 0 1 1 /2 5 system clock/t0 1 0 0 /2 3 system clock/t0 1 0 1 /2 2 system clock/t0 1 1 0 /2 1 system clock/t0 1 1 1 /2 0 system clock/t0 table 2. timer1 mode register ($03) t1m.2 t1m.1 t1m.0 prescaler divide ratio clock source 0 0 0 /2 11 system clock/2.048khz 0 0 1 /2 9 system clock/2.048khz 0 1 0 /2 7 system clock/2.048khz 0 1 1 /2 5 system clock/2.048khz 1 0 0 /2 3 system clock/2.048khz 1 0 1 /2 2 system clock/2.048khz 1 1 0 /2 1 system clock/2.048khz 1 1 1 /2 0 system clock/2.048khz http://www.xinpian.net ceo??rg??[?0ic??[?0surgg:??[?g r? 010-62245566 13810019655
sh69p55a/k55a 23 prescaler system clock t osc sync 8-bit counter tm.2 tm.0 tm.1 /16 t1s 32.768 khz mux 2.048 khz also the clock source of timer0 and timer1 is set in timer control registers, as shown blow: systems register: address bit 3 bit 2 bit 1 bit 0 r/w remarks $02 t0s - - - r/w bit3: t0 signal source select register 0 x x x r/w timer0 sour ce is system clock 1 x x x r/w timer0 source is t0 input clock systems register: address bit 3 bit 2 bit 1 bit 0 r/w remarks $03 t0e - - - r/w bit3: t0 signal edge select register 0 x x x r/w increment on high-to-low transition t0 input 1 x x x r/w increment on low-to-high transition t0 input systems register: address bit 3 bit 2 bit 1 bit 0 r/w remarks $3c0 t1s - - - r/w bit3: t1 signal source select register* 0 x x x r/w timer1 sour ce is system clock* 1 x x x r/w timer1 source is 2.048khz* *: the t1s register is available when the oscillator type is selected as 32.768khz. otherwise, the t1s register must be cleared to ?0?. 7.3. external clock/event t0 as timer0 source when external clock/event t0 input as timer0 source, it is synchronized with the cpu system clock. the external source must follow certain constraints. the system clock samples it in instruction frame cycle. therefore it is necessary to be high ( at least 2 t osc ) and low (at least 2 t osc ). when the prescaler ratio selects /2 0 , it is the same as the system clock input. the requirement is as follows: t0h (t0 high time) 2 * t osc + ? t t0l (t0 low time) 2 * t osc + ? t ; ? t= 20ns when another prescaler ratio is selected, the t0m is scaled by the asynchronous ripple counter and so the prescaler output is symmetrical. then: 2 t0 * n timelow t0 time high t0 = = where: t0 = timer0 input period n = prescaler value the requirement is: tt*2 2 t0*n osc ? + or n t*2t*4 t0 osc ? + so, the limitation is applied to the t0 period time only. the pulse width is not limited by this equation. it is summarized as follows: n t *2t*4 period timer0 t0 osc ? + = http://www.xinpian.net ceo??rg??[?0ic??[?0surgg:??[?g r? 010-62245566 13810019655
sh69p55a/k55a 24 7.4. timer2 timer2 is a 16-bit timer and it has the following features: - 16-bit up-counting timer/counter. - automatic re-load counter. - 8-level prescaler. - interrupt on overflow from $ffff to $0000. the following is a simplified timer2 block diagram. prescaler system clock t osc sync 16-bit counter sc.2 sc.0 sc.1 eor t2e tms1 t2 mux tms0 the timer2 provides the following functions: - programmable interval timer function. - read counter value. 7.5. timer2 configuration and operation timer2 consists of a 16-bit write-only timer load register (tl2l, tl2ml, tl2mh, tl2h) and a 16-bit read-only timer counter (tc2l, tc2ml, tc2mh, tc2h). each of them has low-order digits and high-order digits. writing data into the timer load register (tl2l, tl2ml, tl2mh, tl2h) can initialize the timer counter. the low-order digit should be written first, and then the high-order digit. the timer counter is automatically loaded with the contents of the load register when the high order digit is written or the counter counts overflow from $ffff to $0000. timer load register: since the register h controls the physical read and write operations. please follow these steps: write operation: low nibble first high nibble to update the counter read operation: high nibble first low nibble followed. load reg. h 16-bit timer counter load reg. l latch reg. l latch reg. h 7.6. timer2 control register the timer2 can be programmed in several different modes: timer, external event counter, and external trigger timer and pulse width measurement. timer2 control register: $27 address bit 3 bit 2 bit 1 bit 0 r/w remarks $27 t2go dec tm2s1 tm2s0 r/w bit1-0: timer2 mode select register bit3: set timer2 function start register x x 0 0 r/w timer with internal system clock x x 0 1 r/w event counter with external clock (t2 pin input) x x 1 0 r/w timer with external trigger (t2 pin input) x x 1 1 r/w pulse width measurement (t2 pin input) 0 x x x r/w timer/counter stops (read: status; write: command) (default) 1 x x x r/w timer/counter starts (read: status; write: command) note: before using event counter mode, timer with external trigger mode or pulse width measurement mode, the $3c2 bit3 must be cleared to 0. http://www.xinpian.net ceo??rg??[?0ic??[?0surgg:??[?g r? 010-62245566 13810019655
sh69p55a/k55a 25 (1) timer mode in this mode, timer2 is performed using the internal system clock. the contents of the timer2 load register ($384 - $387) are loaded into the up-counter while the highest nibble ($387) has been written. the up-counter will start counting if the timer2 control register ($27) t2go (bit3) is set to 1. the timer2 interrupt will issue when the up-counter overflows from $ffff to $0000 if the interrupt enable register ($00) iet2 (bit1) is set to 1. after the timer2 control register ($27) t2go (bit3) has been set to 1, writing the timer2 load register ($384 - $387) can not affect the up-counter operating anymore. only when the timer2 control register ($27) t2go (bit3) has been cleared to 0, the contents of the timer2 load register ($384 - $387) will be loaded into the up-counter while the highest nibble ($387) is writte n. timer2 pre-scaler register: $15 address bit 3 bit 2 bit 1 bit 0 r/w remarks $15 t2e t2sc.2 t2sc.1 t2sc.0 r/w bit2-0: timer2 pre-scaler register bit3: t2 external signal edge select register x 0 0 0 r/w timer clock source: f sys /2 11 x 0 0 1 r/w timer clock source: f sys /2 9 x 0 1 0 r/w timer clock source: f sys /2 7 x 0 1 1 r/w timer clock source: f sys /2 5 x 1 0 0 r/w timer clock source: f sys /2 3 x 1 0 1 r/w timer clock source: f sys /2 2 x 1 1 0 r/w timer clock source: f sys /2 1 x 1 1 1 r/w timer clock source: f sys /2 0 0 x x x r/w increment on high-to-low transition t2 input 1 x x x r/w increment on low-to-high transition t2 input (2) external event counter mode in this mode, timer2 is performed using the external clock via t2 pin (shared with portg3). either the rising or falling edge can be selected with the external trigger controlled by the timer2 pre-scaler register ($15) t2e (bit3). the contents of the timer2 load register ($384 - $387) are loaded into the up-c ounter while the highest nibble ($387) has been written. the up-counter will start counting if the timer2 control register ($27) t2go (bit3) is set to 1. the timer2 interrupt will issue wh en the up-counter overflows from $ffff to $0000 if the interrupt enable register ($00) iet2 (bit1) is set to 1. after the timer2 control register ($27) t2go (bit3) has been set to 1, writing the timer2 load register ($384 - $387) can not affect the up-counter operating anymore. only when the timer2 control register ($27) t2go (bit3) has been cleared to 0, the contents of the timer2 load register ($384 - $387) will be loaded into the up-counter while the highest nibble ($387) is writte n. the external clock source must follow certain constraints. the sy stem clock samples it in instru ction frame cycle. therefore it is necessary to be high at least 2 t osc and low at least 2 t osc . in this mode, the pre-scaler circuit will not affect the external clock input. that means the input clock will bypass the pre- scaler circuit and disregards the value in timer2 pre-scaler register. so, the limitation is applied to the external clock period time (t e ) described as follows: t e (period time) 4 * t osc + 2 * ? t ; ? t = 20ns http://www.xinpian.net ceo??rg??[?0ic??[?0surgg:??[?g r? 010-62245566 13810019655
sh69p55a/k55a 26 (3) external trigger timer mode in this mode, the counting is triggered by an external signal via t2 pin (shared with portg3). either the rising or falling edg e can be selected by setting the timer2 pre-scaler register ($15) t2e (bit3). but the clock source of the up-counter is the internal system clock. the contents of the timer2 load register ($384 - $387) are loaded into the up-counter while the highest nibble ($387) has been written. only after the timer2 control register ($27) t2go (bit3) has been set to 1, a valid edge signal on the t2 input pin can start counting. the timer2 interrupt will issue when the up-counter overflows from $ffff to $0000 if the interrupt enable register ($00) iet2 (bit1) is set to 1. wh en the timer2 interrupt is generated the up-counter is halted. t he up-counter is restarted by the next valid edge of the t2 pin input. when the timer2 control register ($27) dec (bit2) is set to 1, a valid rising (falling) edge signal on the t2 input pin can sta rt counting, a valid falling (rising) edge signal on the t2 input pin will stop counting and the contents of the timer2 load regis ter ($384 - $387) are reloaded into the up-counter. inputting a pr oper width pulse can generate interrupts. when the timer2 control register ($27) dec (bit2) is cleared to 0, the reverse directive edge input is ignored. the another valid edge input fr om t2 pin before the up-counter overflowing is also ignored. after the timer2 control register ($27) t2go (bit3) is set to 1, writing the timer2 counter register ($384 - $387) can not affe ct the up-counter operating anymore. only when the timer2 contro l register ($27) t2go (bit3) has been cleared to 0, the contents of the timer2 load register ($384 - $387) will be loaded into the up-counter while the highest nibble ($387) is writte n. the t2 pin input signal must follow certain constraints. the system clock samples it in instruction frame cycle. therefore it i s necessary to be high at least 1/2 t timer clock and low at least 1/2 t timer clock . in this mode, the timer clock is selected by the timer2 pre-scaler register. so, the limitation is applied to the external clock period time (t e ) described as follows: t e (period time) 1 * t timer clock + 2 * ? t ; ? t = 20ns t e (period time) ( m * t osc ) + 2 * ? t where m = 2 3 , 2 4 , 2 5 , 2 6 , 2 8 , 2 10 , 2 12 or 2 14 timer2 control register: $27 (under the external trigger timer mode) address bit 3 bit 2 bit 1 bit 0 r/w remarks $27 t2go dec tm2s1 tm2s0 r/w bit1-0: timer2 mode select register bit2: reverse directive edge input control register x 0 1 0 r/w reverse directive edge input is ignored x 1 1 0 r/w reverse directive edge input reloads internal up-counter timer2 pre-scaler register: $15 (unde r the external trigger timer mode and pulse width measurement mode) address bit 3 bit 2 bit 1 bit 0 r/w remarks $15 t2e t2sc.2 t2sc.1 t2sc.0 r/w bit2-0: timer2 pre-scaler register bit3: t2 external signal edge select x 0 0 0 r/w timer clock source: f sys /2 12 x 0 0 1 r/w timer clock source: f sys /2 10 x 0 1 0 r/w timer clock: source f sys /2 8 x 0 1 1 r/w timer clock: source f sys /2 6 x 1 0 0 r/w timer clock source: f sys /2 4 x 1 0 1 r/w timer clock source: f sys /2 3 x 1 1 0 r/w timer clock source: f sys /2 2 x 1 1 1 r/w timer clock source: f sys /2 1 0 x x x r/w t2 input falling edge active (default) 1 x x x r/w t2 input rising edge active timer2 counter register: $384 - $387 address bit 3 bit 2 bit 1 bit 0 r/w remarks $384 t2d.3 t2d.2 t2d.1 t2d.0 r/w timer2 load/counter low nibble register $385 t2d.7 t2d.6 t2d.5 t2d.4 r/w timer2 load/counter middle_l nibble register $386 t2d.11 t2d.10 t2d.9 t2d.8 r/w timer2 load/counter middle_h nibble register $387 t2d.15 t2d.14 t2d.13 t2d.12 r/w timer2 load/counter high nibble register http://www.xinpian.net ceo??rg??[?0ic??[?0surgg:??[?g r? 010-62245566 13810019655
sh69p55a/k55a 27 t2 internal clock ff9e ffff ff9c ff9d 00 ff9c ff9d ff9f ff9e up-counter t2go timer2 int trigger start (dec = 0) count start count start t2 internal clock f062 m - 1 f060 f061 00 f061 f062 ffff f060 up-counter t2go timer2 int trigger start and stop (dec = 1) count start count start f060 m count relooad (4) pulse width measurement mode in this mode, timer2 is performed using a special function un der the timer mode in which counting is started on an valid edge of pulse that is input to the t2 pin. it is possible to measure the width of the pulse by reading the up-counter values. the rising or falling edge of the t2 pin input is selected by the timer2 pre-scaler register ($15) t2e (bit3). but the clock source of the up-counter is the system internal clock selected by the timer2 pre-scaler register ($15) t2sc (bit2-0). when the timer2 control register ($27) t2go (bit3) is set to 1, the contents of the up-counter is reset to ?0000h?, automatically. then a risin g (falling) edge signal on the t2 input pin triggers the up-counte r to start counting. at the ne xt falling (rising) edge, the cou nter value is loaded to the timer2 load register ($384 - $387), individually. simultaneously, the timer2 interrupt is generated if t he interrupt enable register ($00) iet2 (bit1) is set to 1. when the timer2 control register ($27) dec (bit2) is cleared to 0, the timer2 is in the one-edge capture mode. if the rising edge is selected as the counter-triggering signal, at the next falling edge, the timer2 interrupt request is generated. at the same time, the contents of the up-counter must be loaded to the timer2 load register ($384 - $387) at first, then will be cleared again and the counter is halted. when the next rising edge applies to the t2 input pin, the up-counter starts counting for another measurement cycle. when the timer2 control register ($27) dec (bit2) is set to 1, the timer2 is in the double-edge capture mode. if the rising edge is selected as the counter-triggering signal, at the next falling edge, the timer2 interrupt request is generated. at the same time, the contents of the up-counter must be loaded to the timer2 load register ($384 - $387) at first, then the counter continues counting. when the next rising edge applies to the t2 input pin, the timer2 interrupt request is also generated. at this time, the contents of the up-counter must be loaded to the timer2 load register ($384 - $387) again, then the counter is cleared and can be continued to start counting following measurement cycles. in this mode, writing the timer2 load register ($384 - $387) at any time cannot affect the up-counter operating anymore. in this mode, the t2 pin input signal must follow certain constraints as in the external trigger timer mode. so, the limitation is applied for the external clock period time (t e ) described as follows: t e (period time) 1 * t timer clock + 2 * ? t; ? t = 20ns t e (period time) (m * t osc ) + 2 * ? t http://www.xinpian.net ceo??rg??[?0ic??[?0surgg:??[?g r? 010-62245566 13810019655
sh69p55a/k55a 28 where m (pre-scaler value for timer2 internal clock) = 2 3 , 2 4 , 2 5 , 2 6 , 2 8 , 2 10 , 2 12 or 2 14 but, in order to correctly get the pulse measurement value in programming, a sufficient wait period must be needed for the relevant timer2 interrupt subroutine program. so, if the timer2 control register ($27) dec (bit2) is 0, the ti mer2 is in the one-edge capture mode. the limitation is applied for the external clock period (t e ) time described as follows: t e (period time) 14 * t system clock t e (period time) 14 * 4 * t osc the maximum value of these two equations shown above is valid to the proper application. if the timer2 control register ($27) dec (bit2) is 1, the timer2 is in the double-edge capture operation. the limitation is applied for the t2 input signal high or low level period described as follows: t e (high or low level period time) 14 * t system clock t e (high or low level period time) 14 * 4 * t osc t2 internal clock 0002 0000 0001 n m 0002 n - 1 0000 up-counter t2go timer2 int one edge capture (dec = 0) count start count start 0000 m t2 counter reg. xxxx 0001 n capture capture t2 internal clock 0002 0000 0001 t m 0001 t - 1 t + 1 up-counter t2go timer2 int double edge capture (dec = 1) count start count start m+1 m t2 counter reg. xxxx n t capture capture 0 n capture timer2 control register: $27 (under the pulse width measurement mode) address bit 3 bit 2 bit 1 bit 0 r/w remarks $27 t2go dec tm2s1 tm2s0 r/w bit1-0: timer2 mode select register bit2: capture edge select register x 0 1 1 r/w one edge capture x 1 1 1 r/w double edge capture http://www.xinpian.net ceo??rg??[?0ic??[?0surgg:??[?g r? 010-62245566 13810019655
sh69p55a/k55a 29 8. lcd driver the lcd driver contains a controller, a voltage generator, 4-8 common driver pins/pads and 16-20 segment driver pins/pads. there are three different driving programmable modes: 1/4 duty & 1/3 bias, 1/6 duty & 1/3 bias and 1/8 duty & 1/4 bias. the driving mode is controlled by the system register $29. when 1/4 duty and 1/3 bias mode are used, com8-5 are used as seg17-20. when 1/6 duty and 1/3 bias mode are used, com8-7 are used as seg17-18. the cont roller consists of display data ram and a duty generator. the lcd seg1-20 can also be used as output port, which is selected by the bit2-0 of the system register $2e. when seg1-20 are selected to be output port, one should write data to bit3-0 at the same addresses ($08 - $0c, $38e - $390). the lcd com1-8 can also be used as i/o port (portd, porte), which is selected by bit2 of the system register $29. the lcd com1-6 and seg1-8 can also be shared to led application. lcd ram could be used as data memory if needed. when the ?stop? instruction is executed, the lcd will be turned off, but the data of lcd ram keeps the value. when lcd off, both common and segment output low. before use the lcd driver, leden (bit3 in $2b) must be cleared. lcd control register $29 address bit 3 bit 2 bit 1 bit 0 r/w remarks $29 lcdon duty2 duty1 duty0 r/w bit2-0: set duty and com register bit3: lcd display on control register 0 x x x r/w lcd off 1 x x x r/w lcd on x 0 x x r/w portd and porte as i/o ports x 1 0 0 r/w set 1/4 duty. portd3 - 0 as com1 - 4, porte as i/o ports x 1 0 1 r/w set 1/4 duty. porte3 - 0 as com5 - 8, portd as i/o ports x 1 1 0 r/w set 1/6 duty. portd3 - 0 as com1 - 4, porte3 - 2 as com5 - 6 and porte1 - 0 as i/o ports x 1 1 1 r/w set 1/8 duty. portd3 - 0 as com1 - 4, porte3 - 0 as com5 - 8 lcd frame frequency control register $3c1 address bit 3 bit 2 bit 1 bit 0 r/w remarks $3c1 lps3 lps2 lps1 lps0 r/w lcd frame frequency control register note: 1. if the $3c1 0000b, the lcd frame frequency is controlled by $3c1. com fosc code option osc range lcd frame frequency 00 4m-8m fosc/(20480*(lps+1)) 01 2m-4m fosc/(10240*(lps+1)) 10 1m-2m fosc/(5120*(lps+1)) 11 400k-1m fosc/(2560*(lps+1)) 4 xx 32.768k fosc/(160*(lps+1)) 00 4m-8m fosc/(28672*(lps+1)) 01 2m-4m fosc/(14336*(lps+1)) 10 1m-2m fosc/(7168*(lps+1)) 11 400k-1m fosc/(3584*(lps+1)) 6 xx 32.768k fosc/(224*(lps+1)) 00 4m-8m fosc/(36864*(lps+1)) 10 2m-4m fosc/(18432*(lps+1)) 01 1m-2m fosc/(9216*(lps+1)) 11 400k-1m fosc/(4608*(lps+1)) 8 xx 32.768k fosc/(288*(lps+1)) *: lps = lps3 - lps0 http://www.xinpian.net ceo??rg??[?0ic??[?0surgg:??[?g r? 010-62245566 13810019655
sh69p55a/k55a 30 com1 com1 one frame lcd output frame the following table is the recommended setting. osc clk otp option lps 8com f lcd (hz) lps 6com f lcd (hz) lps 4com f lcd (hz) 8m 00 05h 36 07h 35 0ah 35 7m 00 04h 38 06h 35 0bh 34 6m 00 03h 40 05h 35 07h 36 5m 00 03h 33 04h 35 06h 35 4.0001m 00 02h 36 03h 35 04h 39 4m 01 05h 36 07h 35 0ah 35 3m 01 03h 40 05h 35 07h 36 2.0001m 01 02h 36 03h 35 04h 39 2m 10 05h 36 07h 35 0ah 35 1.0001m 10 02h 36 03h 35 04h 39 1m 11 05h 36 07h 35 0ah 35 500k 11 02h 36 03h 35 04h 39 32.768k xx 02h 38 03h 36 05h 34 2. if the $3c1 = 0000b. the lcd clock is divided from osc, so lcd frame frequency will change in proportion to the variation of osc frequency in spite of osc type and the fosc code option (see page 56 for detail). com fosc code option lcd frame frequency osc range example 00 fosc/40,960 4m - 8m f osc = 4m, f lcd = 97.5hz 01 fosc/20,480 2m - 4m f osc = 2m, f lcd = 97.5hz 10 fosc/10,240 1m - 2m f osc = 1m, f lcd = 97.5hz 11 fosc/5,120 400k - 1m f osc = 500k, f lcd = 97.5hz 4 xx fosc/320 32.768k f osc = 32.768k, f lcd = 102.4hz 00 fosc/57,344 4m - 8m f osc = 4m, f lcd = 69.5hz 01 fosc/28,672 2m - 4m f osc = 2m, f lcd = 69.5hz 10 fosc/14,336 1m - 2m f osc = 1m, f lcd = 69.5hz 11 fosc/7,168 400k - 1m f osc = 500k, f lcd = 69.5hz 6 xx fosc/448 32.768k f osc = 32.768k, f lcd = 73hz 00 fosc/73,728 4m - 8m f osc = 4m, f lcd = 54hz 10 fosc/36,864 2m - 4m f osc = 2m, f lcd = 54hz 01 fosc/18,432 1m - 2m f osc = 1m, f lcd = 54hz 11 fosc/9,216 400k - 1m f osc = 500k, f lcd = 54hz 8 xx fosc/576 32.768k f osc = 32.768k, f lcd = 57hz http://www.xinpian.net ceo??rg??[?0ic??[?0surgg:??[?g r? 010-62245566 13810019655
sh69p55a/k55a 31 3. sh69p55a/69k55a both has lcd driver and led driver, and only one is valid at one time. if leden = 1, the lcd driver is disabled; if leden = 0, the led driver is disabled. seg configuration register: $2e address bit 3 bit 2 bit 1 bit 0 r/w remarks $2e rlcd ps2 ps1 ps0 r/w bit2 - 0: configuration the segment (see the following table) bit3: lcd bias resistor set register ps2 ps1 ps0 pe.3 pe.2 pe.1 pe.0 ph.3 ph.2 ph.1 ph.0 pi.3 pi.2 pi.1 pi.0 pf.3 pf.2 pf.1 pf.0 pa.3 pa.2 pa.1 pa.0 0 0 0 i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o 0 0 1 i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o s5 s4 s3 s2 s1 0 1 0 i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o s6 s5 s4 s3 s2 s1 0 1 1 i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o s7 s6 s5 s4 s3 s2 s1 1 0 0 i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o s8 s7 s6 s5 s4 s3 s2 s1 1 0 1 i/o i/o i/o i/o i/o i/o i/o i/o s12 s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 1 1 0 i/o i/o i/o i/o s16 s15 s14 s13 s12 s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 1 1 1 s20 s19 s18 s17 s16 s15 s14 s13 s12 s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 *sx = segx if the porte3 - 0 are shared as the com5 - 8 for lcd displa y, then the porte3 - 0 cannot shared as the seg20 - 17 for lcd display. segs and coms shall be configured correctly before the lcd is turned on. configuration of lcd ram area: (lcd 1/4 duty, 1/ 3 bias, com uses com1 - 4, seg uses seg1 - 20) bit3 bit2 bit1 bit0 bit3 bit2 bit1 bit0 address com4 com3 com2 com1 address com4 com3 com2 com1 $300 seg1 seg1 seg1 seg1 $30a seg11 seg11 seg11 seg11 $301 seg2 seg2 seg2 seg2 $3 0b seg12 seg12 seg12 seg12 $302 seg3 seg3 seg3 seg3 $ 30c seg13 seg13 seg13 seg13 $303 seg4 seg4 seg4 seg4 $ 30d seg14 seg14 seg14 seg14 $304 seg5 seg5 seg5 seg5 $3 0e seg15 seg15 seg15 seg15 $305 seg6 seg6 seg6 seg6 $30f seg16 seg16 seg16 seg16 $306 seg7 seg7 seg7 seg7 $310 seg17 seg17 seg17 seg17 $307 seg8 seg8 seg8 seg8 $311 seg18 seg18 seg18 seg18 $308 seg9 seg9 seg9 seg9 $312 seg19 seg19 seg19 seg19 $309 seg10 seg10 seg10 seg10 $313 seg20 seg20 seg20 seg20 configuration of lcd ram area: (lcd 1/4 duty, 1/ 3 bias, com uses com5 - 8, seg uses seg1 - 16) bit3 bit2 bit1 bit0 bit3 bit2 bit1 bit0 address com8 com7 com6 com5 address com8 com7 com6 com5 $300 seg1 seg1 seg1 seg1 $308 seg9 seg9 seg9 seg9 $301 seg2 seg2 seg2 seg2 $309 seg10 seg10 seg10 seg10 $302 seg3 seg3 seg3 seg3 $30a seg11 seg11 seg11 seg11 $303 seg4 seg4 seg4 seg4 $3 0b seg12 seg12 seg12 seg12 $304 seg5 seg5 seg5 seg5 $ 30c seg13 seg13 seg13 seg13 $305 seg6 seg6 seg6 seg6 $ 30d seg14 seg14 seg14 seg14 $306 seg7 seg7 seg7 seg7 $3 0e seg15 seg15 seg15 seg15 $307 seg8 seg8 seg8 seg8 $30f seg16 seg16 seg16 seg16 http://www.xinpian.net ceo??rg??[?0ic??[?0surgg:??[?g r? 010-62245566 13810019655
sh69p55a/k55a 32 configuration of lcd ram area: (lcd 1/6 duty, 1/ 3 bias, com uses com1 - 6, seg uses seg1 - 18) bit3 bit2 bit1 bit0 bit3 bit2 bit1 bit0 address com4 com3 com2 com1 address - - com6 com5 $300 seg1 seg1 seg1 seg 1 $320 - - seg1 seg1 $301 seg2 seg2 seg2 seg 2 $321 - - seg2 seg2 $302 seg3 seg3 seg3 seg 3 $322 - - seg3 seg3 $303 seg4 seg4 seg4 seg 4 $323 - - seg4 seg4 $304 seg5 seg5 seg5 seg 5 $324 - - seg5 seg5 $305 seg6 seg6 seg6 seg 6 $325 - - seg6 seg6 $306 seg7 seg7 seg7 seg 7 $326 - - seg7 seg7 $307 seg8 seg8 seg8 seg 8 $327 - - seg8 seg8 $308 seg9 seg9 seg9 seg 9 $328 - - seg9 seg9 $309 seg10 seg10 seg10 seg10 $329 - - seg10 seg10 $30a seg11 seg11 seg11 seg11 $32a - - seg11 seg11 $30b seg12 seg12 seg12 seg12 $32b - - seg12 seg12 $30c seg13 seg13 seg13 seg13 $32c - - seg13 seg13 $30d seg14 seg14 seg14 seg14 $32d - - seg14 seg14 $30e seg15 seg15 seg15 seg15 $32e - - seg15 seg15 $30f seg16 seg16 seg16 seg 16 $32f - - seg16 seg16 $310 seg17 seg17 seg17 seg17 $330 - - seg17 seg17 $311 seg18 seg18 seg18 seg18 $331 - - seg18 seg18 configuration of lcd ram area: (lcd 1/8 duty, 1/ 4 bias, com uses com1 - 8, seg uses seg1 - 16) bit3 bit2 bit1 bit0 bit3 bit2 bit1 bit0 address com4 com3 com2 com1 address com8 com7 com6 com5 $300 seg1 seg1 seg1 seg1 $320 seg1 seg1 seg1 seg1 $301 seg2 seg2 seg2 seg2 $321 seg2 seg2 seg2 seg2 $302 seg3 seg3 seg3 seg3 $322 seg3 seg3 seg3 seg3 $303 seg4 seg4 seg4 seg4 $323 seg4 seg4 seg4 seg4 $304 seg5 seg5 seg5 seg5 $324 seg5 seg5 seg5 seg5 $305 seg6 seg6 seg6 seg6 $325 seg6 seg6 seg6 seg6 $306 seg7 seg7 seg7 seg7 $326 seg7 seg7 seg7 seg7 $307 seg8 seg8 seg8 seg8 $327 seg8 seg8 seg8 seg8 $308 seg9 seg9 seg9 seg9 $328 seg9 seg9 seg9 seg9 $309 seg10 seg10 seg10 seg10 $329 seg10 seg10 seg10 seg10 $30a seg11 seg11 seg11 seg11 $32a seg11 seg11 seg11 seg11 $30b seg12 seg12 seg12 seg12 $32b seg12 seg12 seg12 seg12 $30c seg13 seg13 seg13 seg13 $32c seg13 seg13 seg13 seg13 $30d seg14 seg14 seg14 seg14 $32d seg14 seg14 seg14 seg14 $30e seg15 seg15 seg15 seg15 $32e seg15 seg15 seg15 seg15 $30f seg16 seg16 seg16 seg16 $32f seg16 seg16 seg16 seg16 http://www.xinpian.net ceo??rg??[?0ic??[?0surgg:??[?g r? 010-62245566 13810019655
sh69p55a/k55a 33 lcd power lcd common driver & scan input lcd segment driver & scan output com1 seg1 seg20 lcd power supply control circuit v lcd r1 r2 r3 lcd on com8 - - v1 v2 v3 seg configuration register: $2e address bit 3 bit 2 bit 1 bit 0 r/w remarks $2e rlcd - - - r/w bit3: set lcd bias resistor register 0 x x x r/w r1 = r2 = r3 = 90k 1 x x x r/w r1 = r2 = r3 = 10k x x x x r/w r1 = r2 = r3 = 3k, if keyen = 1 when a large lcd panel is used, user can set the value of $2e to increase the bias current for better lcd performance. but it will cost more power, when the smaller divider resistances are used. when the cpu is in stop mode, the com1-8 and seg1-20 are pulled low. http://www.xinpian.net ceo??rg??[?0ic??[?0surgg:??[?g r? 010-62245566 13810019655
sh69p55a/k55a 34 lcd waveform 1/4 duty, 1/3 bias lcd waveform seg v1 com4 com3 com2 com1 v2 v3 v1 v2 v3 v1 v2 v3 v1 v2 v3 v1 gnd v2 v3 gnd gnd gnd gnd http://www.xinpian.net ceo??rg??[?0ic??[?0surgg:??[?g r? 010-62245566 13810019655
sh69p55a/k55a 35 1/6 duty, 1/3 bias lcd waveform seg v1 com4 com3 com2 com1 v2 v3 v1 v2 v3 v1 v2 v3 v1 v2 v3 v1 gnd v2 v3 gnd gnd gnd gnd http://www.xinpian.net ceo??rg??[?0ic??[?0surgg:??[?g r? 010-62245566 13810019655
sh69p55a/k55a 36 1/8 duty, 1/4 bias lcd waveform v1 v2 v3 gnd v1 v2 v3 gnd v1 v2 v3 gnd v dd v1 v2 v3 gnd seg com3 com2 com1 v dd v dd v dd http://www.xinpian.net ceo??rg??[?0ic??[?0surgg:??[?g r? 010-62245566 13810019655
sh69p55a/k55a 37 9. led driver the led driver contains a controller, 4-6 common driver pins and 8 segment driver pins. ther e are three different driving programmable modes: 1/4 duty, 1/5 duty and 1/6 duty. the driv ing mode is controlled by the system register $2b. the controller consists of display data ram and a duty generator. the led seg1-8 can also be used as output port, which is selected by the bit2-0 of the system register $2e. when seg1-8 are selected to be output port, one should write ?0? to bit2-0 at the address $2e. the led com1-6 can also be used as i/o port (portd, porte), which is selected by bit1-0 of the system register $2b. the built-in led driver has so powerful drive ability that it can drive led direct ly. com can source at least 200ma current. for detail information, please reference the application circuit. before use the led driver, leden must be set to 1. led driver duty control register: $2b address bit 3 bit 2 bit 1 bit 0 r/w remarks $2b leden ledon eduty1 eduty0 r/w bit1-0: set duty register bit2: turn on led driver register bit3: enable led driver register 0 x x x r/w lcd enable 1 x x x r/w led enable 1 0 x x r/w led driver off 1 1 x x r/w led driver on 1 x 0 0 r/w portd and porte are normal i/o port 1 x 0 1 r/w 1/4 duty, portd3 - 0 is shared as com1 - 4 for led display and porte3 - 2 is normal i/o port 1 x 1 0 r/w 1/5 duty, portd3 - 0 and porte3 is shared as com1 - 5 for led display and porte2 is normal i/o port 1 x 1 1 r/w 1/6 duty, portd3 - 0 and porte3 - 2 is shared as com1 - 6 for led display note: sh69p55a/69k55a both has lcd driver and led driver, and just onl y one is valid at one time. if leden = 1, the lcd driver is disabled; if leden = 0, the led driver is disabled. seg configuration register: $2e address bit 3 bit 2 bit 1 bit 0 r/w remarks $2e rlcd ps2 ps1 ps0 r/w bit2-0: configuration the segment register (see the following table) ps2 ps1 ps0 pf3 pf2 pf1 pf0 pa3 pa2 pa1 pa0 0 0 0 i/o i/o i/o i/o i/o i/o i/o i/o 0 0 1 i/o i/o i/o led_s5 led_s4 led_s3 led_s2 led_s1 0 1 0 i/o i/o led_s6 led_s5 led_s4 led_s3 led_s2 led_s1 0 1 1 i/o led_s7 led_s6 led_s5 led_s4 led_s3 led_s2 led_s1 1 0 0 led_s8 led_s7 led_s6 led_s5 led_s4 led_s3 led_s2 led_s1 http://www.xinpian.net ceo??rg??[?0ic??[?0surgg:??[?g r? 010-62245566 13810019655
sh69p55a/k55a 38 configuration of led ram configuration of lcd ram area: (led 1/4 duty, com1 - 4, seg1 - 8) bit3 bit2 bit1 bit0 bit3 bit2 bit1 bit0 address com4 com3 com2 com1 address com4 com3 com2 com1 $300 seg1 seg1 seg1 seg1 $304 seg5 seg5 seg5 seg5 $301 seg2 seg2 seg2 seg2 $305 seg6 seg6 seg6 seg6 $302 seg3 seg3 seg3 seg3 $306 seg7 seg7 seg7 seg7 $303 seg4 seg4 seg4 seg4 $307 seg8 seg8 seg8 seg8 configuration of lcd ram area: (1/5 duty, com1 - 5, seg1 - 8) bit3 bit2 bit1 bit0 bit3 bit2 bit1 bit0 address com4 com3 com2 com1 address - - - com5 $300 seg1 seg1 seg1 seg1 $320 - - - seg1 $301 seg2 seg2 seg2 seg2 $321 - - - seg2 $302 seg3 seg3 seg3 seg3 $322 - - - seg3 $303 seg4 seg4 seg4 seg4 $323 - - - seg4 $304 seg5 seg5 seg5 seg5 $324 - - - seg5 $305 seg6 seg6 seg6 seg6 $325 - - - seg6 $306 seg7 seg7 seg7 seg7 $326 - - - seg7 $307 seg8 seg8 seg8 seg8 $327 - - - seg8 configuration of lcd ram area: (1/6 duty, com1 - 6, seg1 - 8) bit3 bit2 bit1 bit0 bit3 bit2 bit1 bit0 address com4 com3 com2 com1 address - - com6 com5 $300 seg1 seg1 seg1 seg 1 $320 - - seg1 seg1 $301 seg2 seg2 seg2 seg 2 $321 - - seg2 seg2 $302 seg3 seg3 seg3 seg 3 $322 - - seg3 seg3 $303 seg4 seg4 seg4 seg 4 $323 - - seg4 seg4 $304 seg5 seg5 seg5 seg 5 $324 - - seg5 seg5 $305 seg6 seg6 seg6 seg 6 $325 - - seg6 seg6 $306 seg7 seg7 seg7 seg 7 $326 - - seg7 seg7 $307 seg8 seg8 seg8 seg 8 $327 - - seg8 seg8 led waveform select com gnd seg 1/4 duty 1/6 duty v dd select unselect select unselect com gnd select unselect gnd v dd v dd select select select select unselect unselect unselect v dd gnd select unselect seg http://www.xinpian.net ceo??rg??[?0ic??[?0surgg:??[?g r? 010-62245566 13810019655
sh69p55a/k55a 39 10. key scan there is a key scanner built in the sh69p55a/69k55a, which can automatic detect the key-press. it includes four outputs (key_o1 - 4, shared with com1 - com4), five inputs (key_i5 - 1, shared with seg1 - seg5), and it can detect 20 individual keys. the key scan function must be shared with lcd or led fu nction, so the key scan must work in proper lcd or led mode. key scan control register: $28 address bit 3 bit 2 bit 1 bit 0 r/w remarks $28 keynum1 keynum0 keyend keyen r/w r bit0: key scan enable register bit1: key scan end/pr ocessing register bit3 - 2: key scan result register x x x 0 r/w disable key scan x x x 1 r/w enable key scan x x 0 1 r key scan end x x 1 1 r key scan processing x 0 x 1 r no key-press x 1 x 1 r key-press occur 0 x x 1 r one key-press occur, at the same time 1 x x 1 r more than one key-press occur, at the same time key scan data register1: $2c address bit 3 bit 2 bit 1 bit 0 r/w remarks $2c keyc3 keyc2 keyc1 keyc0 r bit3 - 0: th e result of key scan on key_o4 - 1 0 0 0 1 r key-press occur on key_o1 0 0 1 0 r key-press occur on key_o2 0 1 0 0 r key-press occur on key_o3 1 0 0 0 r key-press occur on key_o4 key scan data register2: $2d address bit 3 bit 2 bit 1 bit 0 r/w remarks $2d keyl3 keyl2 keyl1 keyl0 r bit3 - 0: th e result of key scan on key_i5 - 1 0 0 0 0 r key-press occur on key_i1 0 0 0 1 r key-press occur on key_i2 0 0 1 0 r key-press occur on key_i3 0 1 0 0 r key-press occur on key_i4 1 0 0 0 r key-press occur on key_i5 note: 1. if key scan function is shared with lcd function, the lcd function must be selected as 4com, 6com or 8com. it is important that if the lcd function is selected as 4com, portd must be selected as com port (the lcd control register $29 bit2 - 0 can be selected as ?100?, ?110? and ?111?). porta3 - 0, portf0 must be selected as seg output (seg configuration register $2e bit2 - 0 can?t be ?000?). 2. if key scan function is shared with led function, the led func tion must be selected as 4com, 5com or 6com (led driver duty control register $2b bit1 - 0 can be ?01?, ?10? and ?11?). porta3 - 0, portf0 must be selected as seg output (seg configuration register $2e bit2 - 0 can?t be ?000?). 3. in the correct mode, although the lcd or led is turned off, the automatic key scan is also valid. 4. if and only if one key is pressed at the same time, the result of the key scan is valid; otherwise the result of key scan is invalid. http://www.xinpian.net ceo??rg??[?0ic??[?0surgg:??[?g r? 010-62245566 13810019655
sh69p55a/k55a 40 11. analog/digital converter (adc) the 10 channels and 10-bit resolution a/d converter are implemented in this micro-controller. the adc control registers can be used to define the a/d channel number, select analog channel, reference voltage and conversion clock, start a/d conversion, and set the end of a/d conversion flag. the a/d conversion result register byte is read-only. the approach for a/d conversion: - set analog input channels and select the reference voltage. (when using the external reference voltage, please keep in mind that any analog input voltage must not exceed v ref ) - operating adc module and select the converted analog channel. - set a/d conversion clock source. - go/ done = 1, start the a/d conversion. systems register: address bit 3 bit 2 bit 1 bit 0 r/w remarks $13 vrefs acr2 acr1 acr0 r/w bit2-0: a/d port configuration control register bit3: select internal/external reference voltage register x 0 0 0 r/w set analog channels 0 x x x r/w internal reference voltage (v ref = v dd ) 1 x x x r/w external reference voltage systems register: address bit 3 bit 2 bit 1 bit 0 r/w remarks $3c2 acr3 ch3 - - r/w bit2: adc channel control register bit3: a/d port configuration control register 1 x - - r/w set analog channels x 1 - - r/w adc channels control register systems register: address bit 3 bit 2 bit 1 bit 0 r/w remarks $14 adcon ch2 ch1 ch0 r/w bit2-0: adc channel control register bit3: adc module operate control register 0 x x x r/w disable adc module 1 x x x r/w enable adc module set analog channels acr3 acr2 acr1 acr0 9 8 7 6 5 4 3 2 1 0 0 0 0 0 pg1 pg3 pj3 pj2 pj1 pj0 pb3 pb2 pb1 pb0 0 0 0 1 pg1 pg3 pj3 pj2 pj1 pj0 pb3 pb2 pb1 an0 0 0 1 0 pg1 pg3 pj3 pj2 pj1 pj0 pb3 pb2 an1 an0 0 0 1 1 pg1 pg3 pj3 pj2 pj1 pj0 pb3 an2 an1 an0 0 1 0 0 pg1 pg3 pj3 pj2 pj1 pj0 an3 an2 an1 an0 0 1 0 1 pg1 pg3 pj3 pj2 pj1 an4 an3 an2 an1 an0 0 1 1 0 pg1 pg3 pj3 pj2 an5 an4 an3 an2 an1 an0 0 1 1 1 pg1 pg3 an7 an6 an5 an4 an3 an2 an1 an0 1 x x 0 pg1 an8 an7 an6 an5 an4 an3 an2 an1 an0 1 x x 1 an9 an8 an7 an6 an5 an4 an3 an2 an1 an0 note: the analog channels an8 and an9 are shared with digital i/o portg.3 and portg.1. they are also shared with t2 input pin and tone output pin. if user wants to use t2 input function, the control bit acr3 must be clear to 0. if user wants to use tone generator function, the control bits acr3 - 0 can?t be 1xx1b. http://www.xinpian.net ceo??rg??[?0ic??[?0surgg:??[?g r? 010-62245566 13810019655
sh69p55a/k55a 41 adc channels control ch3 ch2 ch1 ch0 remarks 0 0 0 0 adc channel an0 0 0 0 1 adc channel an1 0 0 1 0 adc channel an2 0 0 1 1 adc channel an3 0 1 0 0 adc channel an4 0 1 0 1 adc channel an5 0 1 1 0 adc channel an6 0 1 1 1 adc channel an7 1 x x 0 adc channel an8 1 x x 1 adc channel an9 http://www.xinpian.net ceo??rg??[?0ic??[?0surgg:??[?g r? 010-62245566 13810019655
sh69p55a/k55a 42 systems register for adc data: address bit 3 bit 2 bit 1 bit 0 r/w remarks $3ad - - a1 a0 r adc data low nibble register $3ae a5 a4 a3 a2 r adc data middle nibble register $3af a9 a8 a7 a6 r adc data high nibble register systems register: address bit 3 bit 2 bit 1 bit 0 r/w remarks $2f go/ done tadc1 tadc0 - r/w bit2-1: a/d conversion time control register bit3: adc startup/status flag register x 0 0 x r/w a/d conversion time = 13 t osc * x 0 1 x r/w a/d conversion time = 52 t osc * x 1 0 x r/w a/d conversion time = 208 t osc * x 1 1 x r/w a/d conversion time = 416 t osc * 0 x x x r/w a/d conversion is complete or not in processing 1 x x x r/w set 1 to start a/d conversion, keep go/ done = 1 when a/d conversion is in processing *: t osc is the osc clock. if the pll is enable, t osc is the pll frequency otherwise t osc is the osc clock. a/d coverter v dd portg.2 /v ref input voltage v ref portb.0/an0 portb.1/an1 portb.2/an2 portb.3/an3 portj.0/an4 portj.1/an5 portj.2/an6 portj.3/an7 0000 0001 0010 0011 0100 0101 0110 0111 ch3:ch0 v refs portg.3/an8 1xx0 portg.1/an9 1xx1 a/d converter block diagram notes: - select a/d conversion time, make sure that a/d conversion time R 25 s. - when the a/d conversion is complete, an adc interrupt occurs (if the adc interrupt is enabled). - the analog input channels must have their corresponding pxcr (x = b, j, g) bits selected as inputs. - if select i/o port as analog input, the i/o functions and pull-high resistor are disabled. - bit go/ done is automatically cleared by hardwar e when the a/d conversion is complete. - clearing the go/ done bit during a conversion will abort the current conversion. - the a/d result register will not be updated with the partially completed a/d conversion sample. - 4tosc wait is required before the next acquisition is started. - the adc could keep on working in the halt mode, and would stop automatic while executing ?stop? instruction. - the adc could wake-up the device from the halt mode (if the adc interrupt is enabled). http://www.xinpian.net ceo??rg??[?0ic??[?0surgg:??[?g r? 010-62245566 13810019655
sh69p55a/k55a 43 application notes: when the external reference voltage is selected, the sh69p55a/69k55a adc needs a little current, which is input into sh69p55a/69k55a from the v ref pin to maintain the a/d normal running. the methods that show in figure 1 and figure 2 to set up the external reference voltage are recommended. if the a/d conversion time is between 25 s and 50 s, a capacitance (10 f) can be added between the v ref pin and the gnd pin to provide the current input into the sh69p55a/69k55a from the v ref pin (figure 3). the method that shows in figure 4 also can set up the external reference voltage but the current consume of the hole system will increase obviously (v dd = 5.0v, r1 + r2 = 500 ? , 10ma increases) (the dashed frames in all the figures are 0.1 f capacitances in order to reducing the disturbance in the v ref pin). v dd v dd gnd v ref sh69p55a /69k55a 2k v dd v dd gnd v ref sh69p55a /69k55a figure 1. figure 2. v dd v dd gnd v ref r1 r2 sh69p55a /69k55a v dd v dd gnd v ref r1 r2 sh69p55a /69k55a figure 3. (r1+r2 R 50k ? ) figure 4. (r1+r2 Q 500 ? ) http://www.xinpian.net ceo??rg??[?0ic??[?0surgg:??[?g r? 010-62245566 13810019655
sh69p55a/k55a 44 12. pulse width mo dulation (pwm) the sh69p55a/69k55a consists of one 8+2 bit pwm module. the pwm module can provide the pulse width modulation waveform with the period and the duty being controlled, individually. the pwmc is used to control the pwm module operation with proper clocks. the pwmp is used to contro l the period cycle of the pwm module output. and the pwmd is used to control the duty in the waveform of the pwm module output. systems register$20: pwm control register (pwmc) address bit 3 bit 2 bit 1 bit 0 r/w remarks $20 pwms tck1 tck0 pwm_en r/w bit0: pwm output enable control register bit2-1: pwm clock control register bit3: pwm output mode of duty cycle control register x x x 0 r/w disable pwm (default) x x x 1 r/w enable pwm x 0 0 x r/w pwm clock = t osc * (default) x 0 1 x r/w pwm clock = 2 t osc * x 1 0 x r/w pwm clock = 4 t osc * x 1 1 x r/w pwm clock = 8 t osc * 0 x x x r/w pwm output normal mode of duty cycle (high active) (default) 1 x x x r/w pwm output negative mode of duty cycle (low active) the pwm output pin is shared with portg.0 *: t osc is the osc clock. if the pll is enable, t osc is the pll frequency otherwise t osc is the osc clock. systems register $21 - $22: pwm period control register (pwmp) address bit 3 bit 2 bit 1 bit 0 r/w remarks $21 pp.3 pp.2 pp.1 pp.0 r/w pwm period low nibble register $22 pp.7 pp.6 pp.5 pp.4 r/w pwm period high nibble register pwm output period cycle = [pp.7, pp.0] x pwm clock. when [pp.7, pp.0] = 00h, pwm outputs gnd if the pwms bit is cleared to 0. when [pp.7, pp.0] = 00h, pwm outputs high level if the pwms bit is set to 1. systems register $24 - $26: pwm duty control register (pwmd) address bit 3 bit 2 bit 1 bit 0 r/w remarks $24 - - pdf.1 pdf.0 r/w pwm duty fine-tune bits register $25 pd.3 pd.2 pd.1 pd.0 r/w pwm duty low nibble register $26 pd.7 pd.6 pd.5 pd.4 r/w pwm duty high nibble register average pwm output duty cycle = ([pd.7, pd.0] + [pdf.1, pdf.0]/4) x pwm clock. if [pp.7, pp.0] [pd.7, pd.0], pwm outputs high when the pwms bit is cleared to 0. if [pp.7, pp.0] [pd.7, pd.0], pwm outputs gnd level when the pwms bit is set to 1. http://www.xinpian.net ceo??rg??[?0ic??[?0surgg:??[?g r? 010-62245566 13810019655
sh69p55a/k55a 45 system register $24: pwm duty fine control register (pwmdf) address bit 3 bit 2 bit 1 bit 0 r/w remarks $24 - - pdf.1 pdf.0 r/w bit1-0: pwm duty f fine-tune bits register - - 0 0 r/w duty cycle = [pd.7, pd0] in period cycle0, 1, 2, 3 - - 0 1 r/w duty cycle = [pd.7, pd0]+1 in period cycle0 duty cycle = [pd.7, pd0] in period cycle1, 2, 3 - - 1 0 r/w duty cycle = [pd.7, pd0]+1 in period cycle0, 1 duty cycle = [pd.7, pd0] in period cycle 2, 3 - - 1 1 r/w duty cycle = [pd.7, pd0]+1 in period cycle0, 1, 2 duty cycle = [pd.7, pd0] in period cycle 3 pwmn clock t pwm duty cycle = 7fh x t pwm [pd7, pd0] = 7fh, [pp7, pp0] = c0h pwms = 0 duty cycle duty cycle duty cycle duty cycle duty cycle duty cycle duty cycle duty cycle duty cycle duty cycle duty cycle duty cycle duty cycle duty cycle duty cycle duty cycle duty cycle duty cycle duty cycle [pdf1, pdf0] = 00b [pdf1, pdf0] = 01b [pdf1, pdf0] = 10b [pdf1, pdf0] = 11b = 7fh x t pwm = 7fh x t pwm = 7fh x t pwm = 7fh x t pwm = 7fh x t pwm = 7fh x t pwm = 7fh x t pwm = 80h x t pwm = 80h x t pwm = 80h x t pwm = 80h x t pwm = 7fh x t pwm = 7fh x t pwm = 80h x t pwm = 80h x t pwm = 7fh x t pwm = 80h x t pwm = 80h x t pwm = 80h x t pwm 01 02 03 7f 80 bf c0 01 02 03 7f 80 bf c0 01 02 03 7f 80 bf c0 01 02 03 7f 80 bf c0 01 02 03 7f 80 bf c0 period cycle0 = c0h x t pwm period cycle1 = c0h x t pwm period cycle2 = c0h x t pwm period cycle3 = c0h x t pwm period cycle0 = c0h x t pwm 8+2 bit pwm waveform programming notes: 1. select the pwm module system clock. 2. set the pwm period cycle by writing proper value to the pwm period control register (pwmp). first set the low nibble, then the middle nibble and the last set the high nibble. 3. set the pwm duty cycle by writing proper value to the pwm duty control register (pwmd). first set the fine tune nibble, then the low nibble, then the middle nibble and the last set the high nibble. 4. select the pwm output mode of the duty cycle by writing the pwms bit in the pwm control register (pwmc). 5. to output the desired pwm waveform, enable the pwm module by writing ?1? to the pwm_en bit in the pwm control register (pwmc). 6. if the pwm period cycle or duty cycle is needed to be changed, the writing flow should be followed as described in step 1 or step 2. then the revised data are loaded into the re-load counter and the pwm module starts counting at next period. http://www.xinpian.net ceo??rg??[?0ic??[?0surgg:??[?g r? 010-62245566 13810019655
sh69p55a/k55a 46 note: - if the i/o port (portg.0) is selected as the pwm output, the i/o functions and pull-high resistor are disabled. - the pwm could keep on working in the halt mode, and would stop automatic when the ?stop? instruction is executed. pwm clock t pwm 01 02 03 04 7d 7e 7f 05 80 ef f0 01 02 03 04 pwm output (pwms = 0) pwm output duty cycle = 7fh x t pwm pwm output (pwms = 1) pwm output period cycle = f0h x t pwm [pp.7, pp.0] = f0h [pd.7, pd.0] = 7fh [pdf.1, pdf.0] = 00h pwm output example pwm clock t pwm 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 01 02 03 04 05 06 07 08 write [pp.7, pp.0] = 0dh write [pd.7, pd.0] = 07h pwm output (pwms = 0) period cycle = 0fh x t pwm duty cycle = 06h x t pwm period cycle = 0dh x t pwm duty cycle = 06h x t pwm duty cycle = 07h x t pwm pwm output period or duty cycle changing example http://www.xinpian.net ceo??rg??[?0ic??[?0surgg:??[?g r? 010-62245566 13810019655
sh69p55a/k55a 47 13. low voltage reset (lvr) the lvr function is to monitor the supply voltage and generate an internal reset in the device. it is typically used in ac line applications or large battery where heavy loads may be switched in and cause the device voltage to temporarily fall below the specified operating minimum. the lvr function is selected by the code option. the lvr circuit has the following functions when the lvr function is enabled: - generates a system reset when v dd v lvr - cancels the system reset when v dd > v lvr here, v lvr which is lvr detect voltage has two level select by code option. lvr flag will always keep ?1? when the lvr happens; lvr flag must be cleared to ?0? by software. system register: $17 address bit 3 bit 2 bit 1 bit 0 r/w remarks $17 lvr - - - r/w bit3: low voltage reset flag register (read and write 0 only) 0 x x x r/w no low voltage reset 1 x x x r/w low voltage reset 14. rom data table (rdt) system register: address bit 3 bit 2 bit 1 bit 0 r/w remarks $380 rdt.3 rdt.2 rdt.1 rdt.0 r/w rom data table address/data register $381 rdt.7 rdt.6 rdt.5 rdt.4 r/w rom data table address/data register $382 rdt.11 rdt.10 rdt.9 rdt.8 r/w rom data table address/data register $383 rdt.15 rdt.14 rdt.13 rdt.12 r/w rom data table address/data register the rdt register consists of a 13-bit write-only pc address load register (rdt.12 - rdt.0) and a 16-bit read-only rom table data read-out register (rdt.15 - rdt.0). to read out the rom table data, users should fill 0 to higher 3 bit (bit 15 - 13) first, then write the rom table address to rd t register (high nibble first then low nibble), after one instruction, the right data will put into rdt register automatically (w rite lowest nibble of address into register will start the data read-out action). http://www.xinpian.net ceo??rg??[?0ic??[?0surgg:??[?g r? 010-62245566 13810019655
sh69p55a/k55a 48 15. dual tone sh69p55a/69k55a has two 12-bit tone generators. the tone genera tors generate the specific frequency of tone with square wave. tone generator control register: address bit 3 bit 2 bit 1 bit 0 r/w remarks $3a3 tg1.3 tg1.2 tg1.1 tg1.0 r/w tone generator 1 low nibble register $3a4 tg1.7 tg1.6 tg1.5 tg1.4 r/w tone generator 1 middle nibble register $3a5 tg1.11 tg1.10 tg1.9 tg1.8 r/w tone generator 1 high nibble register $3a6 tg2.3 tg2.2 tg2.1 tg2.0 r/w tone generator 2 low nibble register $3a7 tg2.7 tg2.6 tg2.5 tg2.4 r/w tone generator 2 middle nibble register $3a8 tg2.11 tg2.10 tg2.9 tg2.8 r/w tone generator 2 high nibble register tone generator volume control register: address bit 3 bit 2 bit 1 bit 0 r/w remarks $3a9 tv1.3 tv1.2 tv1.1 tv1.0 r/w tone generator 1 volume low nibble register $3aa tg1en tv1.6 tv1.5 tv1.4 r/w bit2-0: tone generator 1 volume high nibble register bit3: tone generator 1 enable register $3ab tv2.3 tv2.2 tv2.1 tv2.0 r/w tone generator 2 volume low nibble register $3ac tg2en tv2.6 tv2.5 tv2.4 r/w bit2-0: tone generator 2 volume high nibble register bit3: tone generator 2 enable register the volume control register is 7-bit register used to control the output level of the tone generator. tgxen: tone generator x enabl 0: tone generator x disable (default) 1: tone generator x enable note: x = 1 or 2 programming notes: before using tone generators functions, the $3c2 bit3 (acr3) and $13 bit2 - 0(acr2 - acr0) can?t be 1xx1b. while the tone generators are operating, to reduce the power consumption never execute the ?halt? or ?stop? instruction. don?t enable two-tone channels together to produce one tone. or else, it will produce some unpredicted errors. if it is necessary to use 2 channels together (ex. to play two-channel melody), don?t try to keep the score be the same tones as much as possible, then the unpredicted errors will not occur or it will be ignored through user?s hearing. the tone generator outputs frequency is divided from osc frequency, xn fosc frequency output tone 8 = where n = fffh - tgcr (tgx.11 - tgx.0) x = 1 or 2 http://www.xinpian.net ceo??rg??[?0ic??[?0surgg:??[?g r? 010-62245566 13810019655
sh69p55a/k55a 49 music table 1 following is the music scale reference table for the tone generator channel 1 (or channel 2) under osx = 4mhz. note ideal freq. n tgcr (tgx.11 - tgx.0) (x = 1 or 2) real freq. error% note ideal freq. n tgcr (tgx.11 - tgx.0) (x = 1 or 2) real freq. error% b2 123.47 4050 02e 123.46 -0.01 #f5 739.99 676 d5c 739.64 -0.05 c3 130.81 3822 112 130.82 0.01 g5 783.99 638 d82 783.70 -0.04 #c3 138.59 3608 1e8 138.58 -0.01 #g5 830.61 602 da6 830.56 -0.01 d3 146.83 3405 2b3 146.84 0.01 a5 880.00 568 dc8 880.28 0.03 #d3 155.56 3214 372 155.57 0.00 #a5 932.33 536 de8 932.84 0.06 e3 164.81 3034 426 164.80 -0.01 b5 987.77 506 e06 988.14 0.04 f3 174.61 2863 4d1 174.64 0.02 c6 1046.5 478 e22 1046.0 -0.05 #f3 185.00 2703 571 184.98 -0.01 #c6 1108.7 451 e3d 1108.7 -0.01 g3 196.00 2551 609 196.00 0.00 d6 1174.7 426 e56 1173.7 -0.08 #g3 207.65 2408 698 207.64 -0.01 #d6 1244.5 402 e6e 1243.8 -0.06 a3 220.00 2273 71f 219.97 -0.01 e6 1318.5 379 e85 1319.3 0.06 #a3 233.08 2145 79f 233.10 0.01 f6 1396.9 358 e9a 1396.7 -0.02 b3 246.94 2025 817 246.91 -0.01 #f6 1480.0 338 eae 1479.3 -0.05 c4 261.63 1911 889 261.64 0.01 g6 1568.0 319 ec1 1567.4 -0.04 #c4 277.18 1804 8f4 277.16 -0.01 #g6 1661.2 301 ed3 1661.1 -0.01 d4 293.66 1703 959 293.60 -0.02 a6 1760.0 284 ee4 1760.6 0.03 #d4 311.13 1607 9b9 311.14 0.00 #a6 1864.7 268 ef4 1865.7 0.05 e4 329.63 1517 a13 329.60 -0.01 b6 1975.5 253 f03 1976.3 0.04 f4 349.23 1432 a68 349.16 -0.02 c7 2093.0 239 f11 2092.1 -0.05 #f4 369.99 1351 ab9 370.10 0.03 #c7 2217.5 225 f1f 2222.2 0.22 g4 392.00 1276 b04 391.85 -0.04 d7 2349.3 213 f2b 2347.4 -0.08 #g4 415.30 1204 b4c 415.28 -0.01 #d7 2489.0 201 f37 2487.6 -0.06 a4 440.00 1136 b90 440.14 0.03 e7 2637.0 190 f42 2631.6 -0.21 #a4 466.16 1073 bcf 465.98 -0.04 f7 2793.8 179 f4d 2793.3 -0.02 b4 493.88 1012 c0c 494.07 0.04 #f7 2960.0 169 f57 2958.6 -0.05 c5 523.25 956 c44 523.01 -0.05 g7 3136.0 159 f61 3144.7 0.28 #c5 554.37 902 c7a 554.32 -0.01 #g7 3322.4 150 f6a 3333.3 0.33 d5 587.33 851 cad 587.54 0.04 a7 3520.0 142 f72 3521.1 0.03 #d5 622.25 804 cdc 621.89 -0.06 #a7 3729.3 134 f7a 3731.3 0.05 e5 659.26 758 d0a 659.63 0.06 b7 3951.1 127 f81 3937.0 -0.36 f5 698.46 716 d34 698.32 -0.02 c8 4186.0 119 f89 4201.7 0.37 http://www.xinpian.net ceo??rg??[?0ic??[?0surgg:??[?g r? 010-62245566 13810019655
sh69p55a/k55a 50 music table 2 following is the music scale reference table for the tone generator channel 1(or channel 2) under osx = 2mhz. note ideal freq. n tgcr (tgx.11 - tgx.0) (x = 1 or 2) real freq. error% note ideal freq. n tgcr (tgx.11 - tgx.0) (x = 1 or 2) real freq. error% b1 61.73 4050 2e 61.73 0.00 c5 523.25 478 e22 523.01 -0.05 c2 65.10 3840 100 65.10 0.00 #c5 554.37 451 e3d 554.32 -0.01 #c2 69.29 3608 1e8 69.29 0.00 d5 587.33 426 e56 586.85 -0.08 d2 73.42 3405 2b3 73.42 0.00 #d5 622.25 402 e6e 621.89 -0.06 #d2 77.78 3214 372 77.78 0.00 e5 659.26 379 e85 659.63 0.06 e2 82.41 3034 426 82.40 -0.01 f5 698.46 358 e9a 698.32 -0.02 f2 87.31 2863 4d1 87.32 0.01 #f5 739.99 338 eae 739.64 -0.05 #f2 92.50 2703 571 92.49 -0.01 g5 783.99 319 ec1 783.70 -0.04 g2 98.00 2551 609 98.00 0.00 #g5 830.61 301 ed3 830.56 -0.01 #g2 103.82 2408 698 103.82 0.00 a5 880.00 284 ee4 880.28 0.03 a2 110.00 2273 71f 109.99 -0.01 #a5 932.33 268 ef4 932.84 0.06 #a2 116.54 2145 79f 116.55 0.01 b5 987.77 253 f03 988.14 0.04 b2 123.47 2025 817 123.46 -0.01 c6 1046.5 239 f11 1046.0 -0.05 c3 130.81 1911 889 130.82 0.01 #c6 1108.7 225 f1f 1111.1 0.22 #c3 138.59 1804 8f4 138.58 -0.01 d6 1174.7 213 f2b 1173.7 -0.08 d3 146.83 1703 959 146.80 -0.02 #d6 1244.5 201 f37 1243.8 -0.06 #d3 155.56 1607 9b9 155.57 0.00 e6 1318.5 190 f42 1315.8 -0.21 e3 164.81 1517 a13 164.80 -0.01 f6 1396.9 179 f4d 1396.7 -0.02 f3 174.61 1432 a68 174.58 -0.02 #f6 1480.0 169 f57 1479.3 -0.05 #f3 185.00 1351 ab9 185.05 0.03 g6 1568.0 159 f61 1572.3 0.28 g3 196.00 1276 b04 195.92 -0.04 #g6 1661.2 150 f6a 1666.7 0.33 #g3 207.65 1204 b4c 207.64 -0.01 a6 1760.0 142 f72 1760.6 0.03 a3 220.00 1136 b90 220.07 0.03 #a6 1864.7 134 f7a 1865.7 0.05 #a3 233.08 1073 bcf 232.99 -0.04 b6 1975.5 127 f81 1968.5 -0.36 b3 246.94 1012 c0c 247.04 0.04 c7 2093.0 119 f89 2100.8 0.37 c4 261.63 956 c44 261.51 -0.04 #c7 2217.5 113 f8f 2212.4 -0.23 #c4 277.18 902 c7a 277.16 -0.01 d7 2349.3 106 f96 2358.5 0.39 d4 293.66 851 cad 293.77 0.04 #d7 2489.0 100 f9c 2500.0 0.44 #d4 311.13 804 cdc 310.95 -0.06 e 7 2637.0 95 fa1 2631.6 -0.21 e4 329.63 758 d0a 329.82 0.06 f7 2793.8 89 fa7 2809.0 0.54 f4 349.23 716 d34 349.16 -0.02 #f7 2960.0 84 fac 2976.2 0.55 #f4 369.99 676 d5c 369.82 -0.05 g7 3136.0 80 fb0 3125.0 -0.35 g4 392.00 638 d82 391.85 -0.04 #g7 3322.4 75 fb5 3333.3 0.33 #g4 415.30 602 da6 415.28 -0.01 a7 3520.0 71 fb9 3521.1 0.03 a4 440.00 568 dc8 440.14 0.03 #a7 3729.3 67 fbd 3731.3 0.05 #a4 466.16 536 de8 466.42 0.06 b7 3951.1 63 fc1 3968.3 0.44 b4 493.88 506 e06 494.07 0.04 c8 4186.0 60 fc4 4166.7 -0.46 http://www.xinpian.net ceo??rg??[?0ic??[?0surgg:??[?g r? 010-62245566 13810019655
sh69p55a/k55a 51 16. watch dog timer (wdt) watch dog timer is a down-count counter, and its clock source is an independent built-in rc oscillator, so that the wdt will always run even in the stop mode. the watchdog timer automatically generates a device reset when it overflows. it can be enabled or disabled permanently by using the code option. the watchdog timer control bits ($1e bit2 - 0) are used to select different overflow frequency. wdt bit3 is the watchdog timer overflow flag. the watchdog timer overflow flag ($1e bit3) will be automatically set to ?1? by hardware when the watchdog timer overflows. by reading or writing the system register $1e, the watchdog timer should re-count before the overflow happens. system register $1e: watchdog timer (wdt) address bit 3 bit 2 bit 1 bit 0 r/w remarks $1e wdt wdt.2 wdt.1 wdt.0 r/w r bit2-0: watch dog timer control register bit3: watchdog timer overflow flag register (read only) x 0 0 0 r/w watch dog timer-out period = 4096ms x 0 0 1 r/w watch dog timer-out period = 1024ms x 0 1 0 r/w watch dog timer-out period = 256ms x 0 1 1 r/w watch dog timer-out period = 128ms x 1 0 0 r/w watch dog timer-out period = 64ms x 1 0 1 r/w watch dog timer-out period = 16ms x 1 1 0 r/w watch dog timer-out period = 4ms x 1 1 1 r/w watch dog timer-out period = 1ms 0 x x x r no watchdog timer overflow resets 1 x x x r watchdog timer overflow, wdt reset happens note: watchdog timer-out period valid for v dd = 5v. http://www.xinpian.net ceo??rg??[?0ic??[?0surgg:??[?g r? 010-62245566 13810019655
sh69p55a/k55a 52 17. interrupt four interrupt sources are available on sh69p55a/69k55a: - timer0 interrupt - timer1 interrupt - timer2 interrupt - external interrupts (include portb, portc interrupts (falling edge), ad interrupt, key scan interrupt) interrupt control bits and interrupt service the interrupt control flags are mapped on $00 and $01 of the system register. they can be accessed by the program. those flags are cleared to ?0? at initialization by the chip reset. system register: address bit 3 bit 2 bit 1 bit 0 r/w remarks $00 iet0 iet1 iet2 ieex r/w interrupt enable flags register $01 irqt0 irqt1 irqt2 irqex r/w interrupt request flags register when iex is set to ?1? and the interrupt request is generated (irqx is 1), the interrupt will be activated and the vector addre ss will be generated from the priority pla corresponding to the interrupt sources. when an interrupt occurs, the pc and cy flag will be saved into the stack memory and jump to the interrupt service vector address. after the interrupt occurs, all interrupt enable flags (iex) are clear to ?0? automatically, so when irqx is 1 and iex is set to ?1? again, the interrupt will be activat ed and the vector address will be generated from the priori ty pla corresponding to the interrupt sources. instruction execution n instruction execution i1 instruction execution i2 interrupt generated interrupt accepted vector generated stacking fetch vector address reset ie.x start at vector address inst.cycle 12345 interrupt servicing sequence diagram interrupt nesting during the sh6610d cpu interrupt service, the user can enable any interrupt enable flag before returning from the interrupt. the servicing sequence diagram shows the next interrupt and the next nesting interrupt occurrences. if the interrupt request is ready and the instruction of execution n is ie enable, then the interrupt will start immediately after the next two instruct ion executions. however, if instruction i1 or instruction i2 disables the interrupt request or enable flag, then the interrupt serv ice will be terminated. timer (timer0, timer1, timer2) interrupt the input clock of timer0, timer1 and timer2 are based on system clocks or external clock/event t0 input as timer0 source and t2 input as timer2 source. the timer overflow from $ ff to $00 (from $ffff to $0000 fo r timer2) will generate an internal interrupt request (irqt0, irqt1 = 1 or irqt2 = 1), if the interrupt enable flag is enabled (iet0, iet1 = 1 or iet2 = 1 ), a timer interrupt service routine will start. timer interrupt can also be used to wake the cpu from the halt mode. external interrupts external interrupts include portb, portc falling edge inte rrupt; adc interrupt and key scan interrupt. any external interrupt occur, an internal interrupt request (irqex) will be generated, if the interrupt enable flag is enabled (ieex), an external interrupt service routine will start. http://www.xinpian.net ceo??rg??[?0ic??[?0surgg:??[?g r? 010-62245566 13810019655
sh69p55a/k55a 53 ? portb, portc falling edge interrupt the portb and portc are used as external port interrupt so urces. since portb and portc are bit programmable i/os, only when the portb and portc are selected as normal i/o input, the voltage transition from vdd to gnd applying to the digital input port can generate a port interrupt. when they are selected as analog input (such as adc input), port interrupt request cannot be generated. the interrupt control flags are mapped on $388, $38a, $38c of the system register. they can be accessed or tested by the read/write operation. those flags are cleared to 0 at the initialization by the chip reset. port interrupts can be used to wake up the cpu from the halt or the stop mode. port interrupt enable flags register: $388, $38a address bit 3 bit 2 bit 1 bit 0 r/w remarks $388 pbien.3 pbien.2 pbien.1 pbien.0 r/w portb interrupt enable flags register $38a pcien.3 pcien.2 pcien.1 pcien.0 r/w portc interrupt enable flags register pb/cien.n, (n = 0, 1, 2, 3) 0: disable port interrupt. (default) 1: enable port interrupt. port interrupt request flags register: $389, $38b address bit 3 bit 2 bit 1 bit 0 r/w remarks $389 pbif.3 pbif.2 pbif.1 pbif.0 r/w portb interrupt request flags register $38b pcif.3 pcif.2 pcif.1 pcif.0 r/w portc interrupt request flags register pb/cif.n, (n = 0, 1, 2, 3) 0: port interrupt is not presented. (default) 1: port interrupt is presented. only writing these bits to 0 is available. application notes: any one of portb & portc input pin transitions from v dd to gnd would set pbif.x or pcif.x to ?1?, in spite of level of the other pin of portb and portc. if pbien.x (or pcien.x) = 1and ieex = 1, the x of portb (or portc) input pin transitions from v dd to gnd would generate an interrupt request (pbif.x = 1 or pcif.x = 1) and interrupt the cpu, in spite of level of the other pin of portb (or portc). ? adc interrupt when the a/d conversion is complete, it will generate an interrupt request (adif = 1), if the adc interrupt is enabled (adie = 1), an external interrupt service routine will start. the adc interrupt can be used to wake the cpu from halt mode. ? key scan interrupt when the key scan is complete, it will generate an interrupt re quest (keyif = 1), if the key scan interrupt is enabled (keyie = 1), an external interrupt service routine will start. the key scan interrupt can be used to wake the cpu from halt mode. other external interrupt enable flags register: $38c address bit 3 bit 2 bit 1 bit 0 r/w remarks $38c - - keyie adie r/w bit0: adc interrupt enable flag register bit1: key scan interrupt enable flag register other external interrupt request flags register: $38d address bit 3 bit 2 bit 1 bit 0 r/w remarks $38d - - keyif adif r/w bit0: adc interrupt request flag register bit1: key scan interrupt request flag register only writing these bits to 0 is available. http://www.xinpian.net ceo??rg??[?0ic??[?0surgg:??[?g r? 010-62245566 13810019655
sh69p55a/k55a 54 irqex interrupt cpu ieex external interrupt request generator pc.3 - 0 request flag (pcif.3 - 0) pccr.3 - 0 falling edge detector pbien.3 - 0 pb.3 - 0 request flag (pbif.3 - 0) pbcr.3 - 0 falling edge detector adc completion detector adc request flag (adif) adc_on key scan completion detector key_scan request flag (keyif) keyen pcien.3 - 0 adie keyie port (including other external sources) interrupt function block-diagram http://www.xinpian.net ceo??rg??[?0ic??[?0surgg:??[?g r? 010-62245566 13810019655
sh69p55a/k55a 55 18. halt and stop mode after the execution of halt instruction, sh69p55a/69k55a will enter the halt mode. in the halt mode, cpu will stop operating but peripheral circuits (timer0, timer1, timer2, adc, pwm and watchdog timer) will keep status. after the execution of stop instructi on, sh69p55a/69k55a will enter the stop mode. the whole chip (if the osc is not 32.768khz, the oscillator will stop in stop mode. if the osc is 32.768khz, the os cillator on/off in stop mode will be controlled by the register $23) will stop operating without watchdog timer if it is enabled. in the halt mode, sh69p55a/69k55a can be waked up if any interrupt occurs. in the stop mode, sh69p55a/69k55a can be waked up if any port interrupt occurs or watchdog timer overflows (wdt is enabled). when cpu is awaked from the halt/stop by any interrupt source, it will execute the relevant interrupt serve subroutine at first. then the instruction next to halt/stop is executed. 19. warm-up timer the device has a build-in warm-up timer to eliminate unstable state of initial oscillation when o scillator starts oscillating i n the following conditions: a. power-on reset (1) in internal rc oscillator mode, f osc = 4mhz, the warm-up counter prescaler divide ratio is 1/2 13 (8192). (2) in external rc oscillator mode, f osc = 400khz - 8mhz, the warm-up counter prescaler divide ratio is 1/2 13 (8192). (3) in crystal oscillator or ceramic resonator mode, the warm-up counter prescaler divide ratio is 1/2 13 (8192). (4) in 32.768khz mode, the warm-up counter prescaler divide ratio is 1/2 13 (8192). b. wdt reset, lvr reset, pin reset (1) in internal rc oscillator mode, f osc = 4mhz, the warm-up counter prescaler divide ratio is 1/2 7 (128). (2) in external rc oscillator mode, f osc = 400khz - 8mhz, the warm-up counter prescaler divide ratio is 1/2 7 (128). (3) in crystal oscillator or ceramic resonator mode, the warm-up counter prescaler divide ratio is 1/2 12 (4096). (4) in 32.768khz mode, the warm-up counter prescaler divide ratio is 1/2 12 (4096). c. wake up from stop mode (1) in internal rc oscillator mode, f osc = 4mhz, the warm-up counter prescaler divide ratio is 1/2 7 (128). (2) in external rc oscillator mode, f osc = 400khz - 8mhz, the warm-up counter prescaler divide ratio is 1/2 7 (128). (3) in crystal oscillator or ceramic resonator mode, the warm-up counter prescaler divide ratio is 1/2 12 (4096). (4) in 32.768khz mode, the warm-up counter prescaler divide ratio is as follows: system clock 32.768khz in stop warm-up counter prescaler divide ratio on 1/2 7 pll off 1/2 12 on 1/2 2 32.768khz off 1/2 12 http://www.xinpian.net ceo??rg??[?0ic??[?0surgg:??[?g r? 010-62245566 13810019655
sh69p55a/k55a 56 20. code option (a) oscillator type: osc[2:0]: 000 = internal rc oscillator (select osco pin as portc1 and osci pin as portc2 for normal i/o ports.) (default) 001 = external rc oscillator (400khz - 8mhz) (selec t osco pin as portc1 for a normal i/o port.) 010 = ceramic resonator (400khz - 8mhz) 011 = crystal oscillator (400khz - 8mhz) 100 = 32.768khz crystal oscillator (b) watch dog timer: wdt: 0 = enable wdt function. (default) 1 = disable wdt function. (c) low voltage reset: lvr: 0 = disable lvr function. (default) 1 = enable lvr function. (d) lvr voltage range: lvr0: 0 = 4v lvr voltage (default) 1 = 2.5v lvr voltage (e) chip pin reset: rst: 0 = enable (default) 1 = disable (select reset pin as portc3.) (f) osc clock range select: fosc[1:0]: 00 = 4mhz < osc clock <= 8mhz (default) 01 = 2mhz < osc clock <= 4mhz 10 = 1mhz < osc clock <= 2mhz 11 = 400khz < osc clock <= 1mhz http://www.xinpian.net ceo??rg??[?0ic??[?0surgg:??[?g r? 010-62245566 13810019655
sh69p55a/k55a 57 instruction set all instructions are one cycle and one-word instructions. the characteristic is memory-oriented operation. 1. arithmetic and logical instruction 1.1. accumulator type mnemonic instruction code function flag change adc x (, b) 00000 0bbb xxx xxxx ac mx + ac + cy cy adcm x (, b) 00000 1bbb xxx xxxx ac, mx mx + ac + cy cy add x (, b) 00001 0bbb xxx xxxx ac mx + ac cy addm x (, b) 00001 1bbb xxx xxxx ac, mx mx + ac cy sbc x (, b) 00010 0bbb xxx xxxx ac mx + -ac + cy cy sbcm x (, b) 00010 1bbb xxx xxxx ac, mx mx + -ac + cy cy sub x (, b) 00011 0bbb xxx xxxx ac mx + -ac +1 cy subm x (, b) 00011 1bbb xxx xxxx ac, mx mx + -ac +1 cy eor x (, b) 00100 0bbb xxx xxxx ac mx ac eorm x (, b) 00100 1bbb xxx xxxx ac, mx mx ac or x (, b) 00101 0bbb xxx xxxx ac mx | ac orm x (, b) 00101 1bbb xxx xxxx ac, mx mx | ac and x (, b) 00110 0bbb xxx xxxx ac mx & ac andm x (, b) 00110 1bbb xxx xxxx ac, mx mx & ac shr 11110 0000 000 0000 0 ac[3]; ac[0] cy; ac shift right one bit cy 1.2. immediate type mnemonic instruction code function flag change adi x, i 01000 iiii xxx xxxx ac mx + i cy adim x, i 01001 iiii xxx xxxx ac, mx mx + i cy sbi x, i 01010 iiii xxx xxxx ac mx + -i +1 cy sbim x, i 01011 iiii xxx xxxx ac, mx mx + -i +1 cy eorim x, i 01100 iiii xxx xxxx ac, mx mx i orim x, i 01101 iiii xxx xxxx ac, mx mx | i andim x, i 01110 iiii xxx xxxx ac, mx mx & i 1.3. decimal adjust mnemonic instruction code function flag change daa x 11001 0110 xxx xxxx ac, mx decimal adjust for add cy das x 11001 1010 xxx xxxx ac, mx decimal adjust for sub cy http://www.xinpian.net ceo??rg??[?0ic??[?0surgg:??[?g r? 010-62245566 13810019655
sh69p55a/k55a 58 2. transfer instruction mnemonic instruction code function flag change lda x (, b) 00111 0bbb xxx xxxx ac mx sta x (, b) 00111 1bbb xxx xxxx mx ac ldi x, i 01111 iiii xxx xxxx ac, mx i 3. control instruction mnemonic instruction code function flag change baz x 10010 xxxx xxx xxxx pc x if ac = 0 bnz x 10000 xxxx xxx xxxx pc x if ac 0 bc x 10011 xxxx xxx xxxx pc x if cy = 1 bnc x 10001 xxxx xxx xxxx pc x if cy 1 ba0 x 10100 xxxx xxx xxxx pc x if ac (0) = 1 ba1 x 10101 xxxx xxx xxxx pc x if ac (1) = 1 ba2 x 10110 xxxx xxx xxxx pc x if ac (2) = 1 ba3 x 10111 xxxx xxx xxxx pc x if ac (3) = 1 call x 11000 xxxx xxx xxxx st cy; pc +1 pc x (not include p) rtnw h, l 11010 000h hhh llll pc st; tbr hhhh; ac illl rtni 11010 1000 000 0000 cy, pc st cy halt 11011 0000 000 0000 stop 11011 1000 000 0000 jmp x 1110p xxxx xxx xxxx pc x (include p) tjmp 11110 1111 111 1111 pc (pc11-pc8) (tbr) (ac) nop 11111 1111 111 1111 no operation where, pc program counter i immediate data ac accumulator logical exclusive or -ac complement of accumulator | logical or cy carry flag & logical and mx data memory bbb ram bank p rom page b ram bank st stack tbr table branch register http://www.xinpian.net ceo??rg??[?0ic??[?0surgg:??[?g r? 010-62245566 13810019655
sh69p55a/k55a 59 in system programming note for otp the in system programming technology is valid for otp chip (sh69p55a). the programming interface of the otp chip must be set on the user?s application pcb, and users can assemble all components including the otp chip in the application pcb before programming the otp chip. of course, it?s accessible bonding otp chip only first, and then programming code and finally assembling other components. since the programming timing of programming interface is very sensitive, therefore four jumpers are needed (v dd , v pp , sda, sck) to separate the programming pins from the application circuit as shown in the following diagram. for few otp chip with more v dd pads, the v dd pads should be connected together. otp chip v pp v dd sck sda gnd to application circuit jumper application pcb otp writer the recommended step is the followings: (1) the jumper is open to separate the programming pins from the application circuit before programming the chip. (2) connect the programming interface with otp writer and begin programming. (3) disconnect otp writer and shorten these jumpers when programming is completed. for more detail information, please refer to the otp writer user manual. http://www.xinpian.net ceo??rg??[?0ic??[?0surgg:??[?g r? 010-62245566 13810019655
sh69p55a/k55a 60 electrical characteristics absolute maximum ratings* dc supply voltage . . . . . . . . . . . . . . . . . . . -0.3v to +7.0v input voltage . . . . . . . . . . . . . . . . . . . .-0.3v to v dd + 0.3v operating ambient temperature . . . . . . . . .-40c to +85c storage temperature . . . . . . . . . . . . . . . -55c to +125c *comments stresses above those listed under " absolute maximum ratings " may cause permanent damage to this device. these are stress ratings only. functional operation of this device at these or any other conditions exceed those indicated in the operational sections of this specification is not implied or intended. exposure to the absolute maximum rating conditions for extended periods may affect device reliability. dc electrical characteristics (v dd = 2.4 - 5.5v gnd = 0v, t a = -40c to +85c, unless otherwise specified.) parameter symbol min. typ. max. unit condition 4.5 5.0 5.5 v 30khz f osc 8mhz operating voltage v dd 2.4 5.0 5.5 v 30khz f osc 4mhz 3.8 - 4.2 v lvr (4v) enable low voltage reset voltage v lvr 2.3 - 2.7 v lvr (2.5v) enable - 2 3 ma f osc = 8mhz, v dd = 5.0v all output pins unloaded, execute nop instruction (wdt off, adc disable, lvr off, lcd off, key scan disable) - 1.0 1.5 ma f osc = 4mhz, v dd = 5.0v all output pins unloaded, execute nop instruction (wdt off, adc disable, lvr off, lcd off, key scan disable) operating current i op 12 20 a f osc = 32.768khz, v dd = 5.0v all output pins unloaded, execute nop instruction (wdt off, adc disable, lvr off, lcd off, key scan disable) - - 1.8 ma f osc = 8mhz, v dd = 5.0v all output pins unloaded (all input pins is not floating) cpu stop (halt mode), wdt off, lvr off, lcd off - - 1.3 ma f osc = 4mhz, v dd = 5.0v all output pins unloaded (all input pins is not floating) cpu stop (halt mode), wdt off, lvr off, lcd off stand by current1 (halt) i sb1 8 15 a f osc = 32.768khz, v dd = 5.0v all output pins unloaded (all input pins is not floating) cpu stop (halt mode), wdt off, lvr off, lcd off - - 10 a f osc = 32.768khz v dd = 5.0v all output pins unloaded (all input pins is not floating) cpu stop (stop mode) wdt off, adc disable lcd off, 32.768khz on stand by current2 (stop) i sb2 - - 1 a v dd = 5.0v all output pins unloaded (all input pins is not floating) cpu stop (stop mode) lcd off, lvr off, wdt off gnd - v dd x 0.3 v i/o ports pins tri-state input low voltage v il gnd - v dd x 0 . 2 v reset , t0, t2, osci (schmitt trigger) v dd x 0.7 - v dd v i/o ports, pins tri-state input high voltage v ih v dd x 0.8 - v dd v reset , t0, t2, osci (schmitt trigger) input leakage current i il -1 - 1 a i/o ports, v in = v dd or gnd pull-high resistor r ph - 30 - k? pull-high resistor (v dd = 5.0v) http://www.xinpian.net ceo??rg??[?0ic??[?0surgg:??[?g r? 010-62245566 13810019655
sh69p55a/k55a 61 dc electrical characteristics (continued) (v dd = 2.4 - 5.5v gnd = 0v, t a = -40c to +85c, unless otherwise specified.) parameter symbol min. typ. max. unit condition output high voltage v oh v dd - 0.7 - - v i/o ports, i oh = -10ma (v dd = 5.0v) v ol - - gnd + 0.6 v i/o ports, i ol = 20ma (exclude portd, porte.2-3, v dd = 5.0v) output low voltage - - gnd + 1.5 v i/o ports, i ol = 200ma (portd, porte.2-3, v dd = 5.0v) wdt current i wdt - - 20 a v dd = 5.0v lcd driving on resistor r on - 5 - k? lcd comx, lcd segx, the voltage variation of v1, v2, v3, is less than 0.2v lcd voltage divider resistor r lcd - 90 10 - k? rlcd = 0 rlcd = 1 note: max. current into v dd = 200ma max. current out of v ss = 250ma ? : data in ?typ.? column is at 5.0v, 25c, unless otherwise specified. ac electrical characteristics (v dd = 2.4v - 5.5v, gnd = 0v, t a = 25c, unless otherwise specified.) parameter symbol min. typ. max. unit condition instruction cycle time t cy 0.5 - 133.4 s 30khz f osc 8mhz t0/t2 input width t iw (t cy + 40)/n - - ns n = prescaler divide ratio input pulse width t ipw t iw /2 - - ns reset pulse width t reset 10 - - s low active v dd = 5.0v wdt period t wdt 1 - - ms v dd = 5.0v pll frequency variation |? f|/f 0.6 % average frequency of continuous 256 clocks frequency stability (rc) |? f|/f - - 15 % external r osc oscillator, include chip-to-chip variation (v dd = 5v, t a = 25c) frequency stability (rc) |? f|/f - - 5 % internal r osc oscillator, f osc = 4mhz. include chip-to-chip variation (v dd = 5v, t a = 25c) a/d converter electrical characteristics (v dd = 2.4v - 5.5v, gnd = 0v, t a = 25c, f osc = 30khz - 8mhz, unless otherwise specified.) parameter symbol min. typ. max. unit condition resolution n r - 10 - bit gnd v ain v ref reference voltage v ref 2.4 - v dd v a/d input voltage v ain gnd - v ref v a/d input resistor r ain 2 1000 - m? v in = 5.0v a/d conversion current i ad - 1 3 ma a/d converter module operating, v dd = 5.0v a/d input current i adin 10 a v dd = 5.0v differential linearity error d le - - 1 lsb v ref = v dd = 5.12v, f osc = 8mhz integral linearity error i le 2 lsb v ref = v dd = 5.12v, f osc = 8mhz full scale error e f - 3 - lsb v ref = v dd = 5.12v, f osc = 8mhz offset error e z - 0.5 2 lsb v ref = v dd = 5.12v, f osc = 8mhz total absolute error e ad - 3 - lsb v ref = v dd = 5.12v, f osc = 8mhz conversion time t con 25 - - s 10 bit resolution and f osc = 8mhz http://www.xinpian.net ceo??rg??[?0ic??[?0surgg:??[?g r? 010-62245566 13810019655
sh69p55a/k55a 62 timing waveform (a) system clock timing waveform t1 t2 t3 t4 t5 t6 t7 t8 t1 t2 t3 t4 f osc system clock t cy (b) t0/t2 input waveform t iw t ipw(l) t ipw(h) t0/t2 input signal http://www.xinpian.net ceo??rg??[?0ic??[?0surgg:??[?g r? 010-62245566 13810019655
sh69p55a/k55a 63 rc oscillator characteristics graphs (for reference only) (a) external rc oscillator resistor vs. frequency: typical rc oscillator re sistor vs. frequency (v dd = 5v) 0 1 2 3 4 5 6 7 8 1 10 100 typical rc oscillator resistance: rosc (k ? ) frequency: fosc (mhz) (b) external rc oscillator oper ation voltage vs. frequency: external rc oscillator o peration voltage vs. frequency (rosc = 7.5k ?) 6.2 6.3 6.4 6.5 6.6 6.7 012345678 external rc oscillator operation voltage:v dd (v) frequency: fosc (mhz) http://www.xinpian.net ceo??rg??[?0ic??[?0surgg:??[?g r? 010-62245566 13810019655
sh69p55a/k55a 64 application circuit (for reference only) ap1: (1) operating voltage: 5.0v (2) oscillator: crystal 8mhz (3) porta, portf: led seg1-8. portd, porte.3, porte.2: ledcom1-6. porta, portd are shared as keyscan ports. portg.1 is used as tone output. porti.0 is used as zero cross detect function for ac power line. portg.0 is used as pwm output. portb are used as adc ports. sh69p55a/69k55a v dd osci /portc2 osco /portc1 v dd 10uf 10k 8mhz c3 = 12p reset c4 = 12p 0.1uf /portc3 gnd porta.0 porta.2 porta.1 porta.3 portf.0 portf.2 portf.1 portf.3 portd.0 portd.2 portd.1 portd.3 porte.3 porte.2 portg.1 portb porti0 ac power adc input v dd r2 = 1k q1 speaker r3 = 1m zero detect for ac power line pwm output r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 portg.0 47k x 4 47k x5 2k x 8 0.1uf http://www.xinpian.net ceo??rg??[?0ic??[?0surgg:??[?g r? 010-62245566 13810019655
sh69p55a/k55a 65 ap2: (1) operating voltage: 5.0v (2) oscillator: crystal 8mhz (3) porta, portf: lcd seg1-8. portd: lcd com1-4. porta, portd are shared as keyscan ports. portg.1 is used as tone output. portk.0 is used as zero cross detect function for ac power line. portg.0 is used as pwm output. portb are used as adc ports. v dd osci /portc2 osco /portc1 reset /portc3 gnd seg1 seg3 seg2 seg4 seg5 seg7 seg6 seg8 com1 com3 com2 com4 portg.1 portb portk.0 portg.0 lcd r4 r5 r6 r7 r8 r9 r10 r11 r12 v dd 10uf 10k 8mhz c3 = 12p c4 = 12p 0.1uf ac power adc input r3 = 1m zero detect for ac power line pwm output v dd r2 = 1k q1 speaker 47k x 4 47k x 5 sh69p55a/69k55a 0.1uf http://www.xinpian.net ceo??rg??[?0ic??[?0surgg:??[?g r? 010-62245566 13810019655
sh69p55a/k55a 66 ordering information part no. package sh69p55af/SH69K55Af 44 qfp sh69p55am/SH69K55Am 28 sop sh69p55a/SH69K55A 32 dip http://www.xinpian.net ceo??rg??[?0ic??[?0surgg:??[?g r? 010-62245566 13810019655
sh69p55a/k55a 67 package information qfp 44 outline dimensions unit: inch/mm 23 33 b e a a 2 a 1 44 34 1 11 12 22 d y g d see detail f seating plane l g d ~ ~~ l 1 c detail f d h d e h e g e symbol dimensions in inches dimensions in mm a 0.106 max. 2.70 max. a 1 0.01 min.0.02max. 0.25 min.0.50max. a 2 0.079+0.008 2.00+0.2 -0.004 -0.1 b 0.012 typ. 0.30 typ. c 0.006 0.002 0.15 0.05 d 0.394 0.004 10.00 0.10 e 0.394 0.004 10.00 0.10 e 0.031 typ. 0.80 typ. g d 0.488 nom. 12.40 nom. g e 0.488 nom. 12.40 nom. h d 0.519 0.008 13.20 0.20 h e 0.519 0.008 13.20 0.20 0.035 +0.002 0.88 +0.05 l -0.006 -0.15 l 1 0.063 typ. 1.60 typ. y 0.004 max. 0.10 max. 0 - 7 0 - 7 notes: 1. dimensions d and e do not include resin fins. 2. dimensions g d & g e are for pc board surface mount pad pitch design reference only. http://www.xinpian.net ceo??rg??[?0ic??[?0surgg:??[?g r? 010-62245566 13810019655
sh69p55a/k55a 68 sop (w.b.) 28l outline dimensions unit: inches/mm 1 e h e l l e c 14 see detail f detail f b 15 28 e 1 e 1 a 1 a 2 a s d seating plane d y e ~ ~~ symbol dimensions in inches dimensions in mm a 0.110 max. 2.79 max. a 1 0.004 min. 0.10 min. a 2 0.093 0.005 2.36 0.13 0.016 +0.004 0.41 +0.10 b -0.002 -0.05 0.010 +0.004 0.25 +0.10 c -0.002 -0.05 d 0.705 0.020 17.91 0.51 e 0.291 - 0.299 7.39 - 7.59 e 0.050 0.006 1.27 0.15 e 1 0.376 nom. 9.40 nom. h e 0.394 - 0.417 10.01 - 10.60 l 0.036 0.008 0.91 0.20 l e 0.055 0.008 1.40 0.20 s 0.043 max. 1.09 max. y 0.004 max. 0.10 max. 0 - 10 0 - 10 notes: 1. the maximum value of dimension d includes end flash. 2. dimension e does not include resin fins. 3. dimension e 1 is for pc board surface mount pad pitch design reference only. 4. dimension s includes end flash. http://www.xinpian.net ceo??rg??[?0ic??[?0surgg:??[?g r? 010-62245566 13810019655
sh69p55a/k55a 69 p-dip 32l outline dimensions unit: inches/mm 1 32 e 1 s a 2 al e e a d c b 1 b a 1 base plane seating plane 16 17 e 1 symbol dimensions in inches dimensions in mm a 0.210 max. 5.33 max. a 1 0.010 min. 0.25 min. a 2 0.155 0.010 3.94 0.25 b 0.018+0.004 0.46+0.10 -0.002 -0.05 b 1 0.050+0.004 1.27+0.10 -0.002 -0.05 c 0.010+0.004 0.25+0.11 -0.002 -0.05 d 1.650 typ. (1.670 max.) 41.91 typ. (42.42 max.) e 0.600 0.010 15.24 0.25 e 1 0.550 typ. (0.562 max.) 13.97 typ. (14.27 max.) e 1 0.100 0.010 2.54 0.25 l 0.130 0.010 3.30 0.25 0 - 15 0 - 15 e a 0.655 0.035 16.64 0.89 s 0.090 max. 2.29 max. notes: 1. the maximum value of dimension d includes end flash. 2. dimension e 1 does not include resin fins. 3. dimension s includes end flash. http://www.xinpian.net ceo??rg??[?0ic??[?0surgg:??[?g r? 010-62245566 13810019655
sh69p55a/k55a 70 data sheet revision history version content date 2.1 ordering information updated dec. 2008 2.0 ordering information updated mar. 2008 1.0 original jan. 2008 http://www.xinpian.net ceo??rg??[?0ic??[?0surgg:??[?g r? 010-62245566 13810019655

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